According to the image from [https://jlcpcb.com/capabilities/Capabilities](https://jlcpcb.com/capabilities/Capabilities) under **Panelization**:
[https://jlcpcb.com/client/image/pcbCapabilities/panelization1.139771a9.jpg](https://jlcpcb.com/client/image/pcbCapabilities/panelization1.139771a9.jpg)
![](https://jlcpcb.com/client/image/pcbCapabilities/panelization1.139771a9.jpg)
it would seem to be OK but I have a PCB ready to submit and before I do I wanted to check if it is OK to have a slot in the PCB that crosses a V-Cut line like where the little hand is on the left in the image below?
![image.png](//image.easyeda.com/pullimage/DbHjFnjIg4O0bT5YwkCRPwtB0SjbkCDKSEYRLUoQ.png)
Chrome
81.0.4044.138
Ubuntu
EasyEDA
6.4.0