@lyseoy, "...it appears that around 90% of the thermal vias are not plated." Please clarify what you mean by "plated". Maybe you misunderstand the structure and appearance of Vias? They are Vias, not Multi-Layer Pads. 1. Like Multi-Layer Pads, they are through-plated 2. Unlike Multi-Layer Pads, Vias do not have exposed copper annuli (the exposed copper area around the central, through plated hole). They are therefore covered with solder resist. On your board this it the green outer coating. 3. Note that the solder resist does not cover the central hole, i.e. the Vias are not tented. 4. Some however, look as if they are or have been (see pictures below) unintentionally tented. 5. Vias are seamlessly joined to any surrounding copper on the same net, they do not "spoke" with thermal reliefs. From your photo it is not possible to see the through plating. * What your photo does show is that the solder resist around some of the Vias appears to be thinner and so looks paler than the surrounding resist.  There are also what appear to be some small areas of exposed copper near some of the Vias:  In both cases it looks like the solder resist has formed bubbles around the Via holes which have then collapsed later leaving thinner areas or tiny pin-holes in the resist around the affected holes. Some of the Via holes appear to have a meniscus of solder resist inside them. "They are designed to have diameter 0.61mm and drill diameter" It looks like there are some words missing. Please clarify this statement.

Hello As about the following questions: > 1\. Is the plating indeed missing from all these vias\,  or is some optical illusion at play? You could confirm the connection by continuity test (short test) between any two points connected through Vias, otherwise we welcome to see a screenshot of your PCB design layout showing the Vias, at JLCPCB we do test connection through flying probes so basically if these Vias are not plated then it will not achieve the flying probe test, since it is successfully delivered to you it means there is no problem with it, but we can help on investigation this so please do a short-circuit test using a multi meter in diode mode and let us know the results. > 2\. Should I have used larger diameter vias for better results? What should be the minimum diameter? No need to go for smaller Via diameter since the ones that you used matches our [capabilities ](https://jlcpcb.com/capabilities/Capabilities): ) If you are willing to know the minimum acceptable Via diameter then you need to specify the number of PCB layers of your design or you can just verify t by yourself through our capabilities page here: [https://jlcpcb.com/capabilities/Capabilities](https://jlcpcb.com/capabilities/Capabilities) You said that the diameter value for your Vias is 0.61 well! this looks familiar for me and I think that you are using EasyEDA as design tool : ) Yet you can get your Via exposed (just like multilayer pad) by specifying this in the Via settings as it shows the below image, sure if this is the purpose for your application. Maybe you want to consider that exposed vias are exposed electrical connections that are not covered with solder mask. Leaving the vias exposed without soldermask does not mean the copper will be open to the environment. The exposed vias will be plated by the surface finish of the PCB. At JLCPCB we use the HASL or ENIG finish which will cover the insides of exposed vias with tin or gold, protecting the copper from corrosion and damage. 

"...please do a short-circuit test using a multi meter in diode mode and let us know the results." This is ok for a single via in a track but unless they are all open circuit, is unlikely to work for the vias in question without highly specialised probing and measurement techniques because there are many of them in parallel in a large copper area.

@lyseoy, @JLCPCBsupport, My bad. When I stated: "...Multi-Layer Pads, Vias do not have exposed copper annuli (the exposed copper area around the central, through plated hole). They are therefore covered with solder resist. On your board this it the green outer coating." I forgot that vias have an **Expose Copper** option as JLCPCBsupport pointed out. From the photo however it appears that this option was not applied on this board. <br> <br>

@andyfierman "They are designed to have diameter 0.61mm and drill diameter" This is what I meant:  OK, so as I have been made aware, vias should be covered by solder resist. (makes sense when you think about it...) So the questions should have been: Why aren't some vias covered by solder resist? What is interesting is these vias are missing the solder resist on both sides of the board. This is very consistent: I have yet to find an exception @JLCPCBsupport It should look familiar! I chose those settings based on some recommendations I found for maximizing heat transfer through vias, and adjusted these according to EasyEDA's standards :-) So just to confirm, should I expect some vias to not be covered with solder resist for larger diameters also?

@lyseoy, "Why aren't some vias covered by solder resist?" Check in the PCB Editor to see if you set the Expose Copper option; Check them in the PCB Editor to see if they are exposed in the Solder Mark Layer; Check them in the Gerber files to see if they are exposed in the Solder Mark Layer. I don't think any of them are not covered by solder resist. If they were not covered by solder resist then they would be tinned like other pads and so would be shiny instead of pale green. As I said above, from your photo above it looks like they all meant to are covered in solder resist and none of them are properly exposed as they would be if the Expose Copper option had been applied but that some of them have had the amount of solder mask on them reduced by bubbles forming over them. "So just to confirm, should I expect some vias to not be covered with solder resist for larger diameters also?" A Via should only have exposed copper if you set the Expose Copper Option for it. The Expose Copper option is applied on a per-Via basis: it is not a global setting.