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Using vias to connect to pads

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dbrouwer 3 years ago

I've tried to find the answer to this in the tutorials and in the forum, but I haven't been able to. Will vias that connect directly to pads cause any issues in assembly, or is it better practice to put the via outside the pad and connect it with a trace to the pad? ![image.png](//image.easyeda.com/pullimage/9h08mdfLApwClzbiZmxekIWtNnZcjbg97naW3Wgw.png)

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Comments

andyfierman 3 years ago

That's a question for whoever you choose for your your PCB manufacturer.

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andyfierman 3 years ago

This is quite a good article but bear in mind that some of the techniques described are not supported by EasyEDA or JLCPCB: [https://community.cadence.com/CSSharedFiles/forums/storage/27/1324522/screaming_5myths.pdf](https://community.cadence.com/CSSharedFiles/forums/storage/27/1324522/screaming_5myths.pdf)

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dbrouwer 3 years ago

Thanks Andy. Since the design I'm working on is quite crowded, using a via to connect to a pad from the opposite side of the board is quite a help in some places. How I'm doing it typically is like the 2 pads on the left ![image.png](//image.easyeda.com/pullimage/uLjSgh4moVXhwoJagdYhwvb4XXEX6t8wPaAYz3ry.png) I am having my boards made by JLCPCB. Could they or anyone else advise me on the question of solder wicking away and down those vias?

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andyfierman 3 years ago

You might like to change the Category of your topic to JLCPCB. :)

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dbrouwer 3 years ago

Thanks Andy!

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JLCPCBsupport 3 years ago

@dbrouwer Hello ; This design method always had some impact, JLCPCB follows the IPC standard for solderability and assembly and in some cases reducing the spot (pad) size in not suitable in assembly because the Via will occupy some space which reduces the contact (lead to pad) surface. But there is no exact instruction to tell in which case the component will not be assembled, so you can follow your design and upload it to our ordering system and check the DFM results.

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