Via inside pad
1360 8
tounho 6 months ago
Can JLCPCB do vias inside pads? There is solder mask on the opposite side of the pad. Will JLCPBB plug the vias or will the solder mask on the opposite side plug the via sufficiently? See image below. A .6mm .3mm via inside a 603 pad. ![via inside pad.png](//image.easyeda.com/pullimage/e8Pdksno5cyyTtoU8WeU5t1gXQWNs0i1AhfmDLZ4.png) Thanks in advance.
Comments
andyfierman 6 months ago
"There is solder mask on the opposite side of the pad." That is only true if you set a suitable negative soldermask expansion (there are posts about this in the Forum). Using the default settings there is no solder mask over any pads in EasyEDA. Adding vias into pads is not good practice as it can suck solder away from the joint by capillary action. AFAIK, JLCPCB does not support tented vias. * Please clarify what you wish to achieve. For information about adding vias to pads for reduced electrical or thermal resistance, please read:  [https://easyeda.com/forum/topic/How-to-avoid-DRC-errors-when-connecting-to-PCB-Footprints-a-k-a-PCB-Libs-90bf944fe3644b21a7d27a9e9d8df8d6](https://easyeda.com/forum/topic/How-to-avoid-DRC-errors-when-connecting-to-PCB-Footprints-a-k-a-PCB-Libs-90bf944fe3644b21a7d27a9e9d8df8d6) which includes a pointer to: [https://easyeda.com/forum/topic/How-to-place-multiple-vias-in-a-PCB-footprint-a34cf68d58414138898a56de60abd8c1](https://easyeda.com/forum/topic/How-to-place-multiple-vias-in-a-PCB-footprint-a34cf68d58414138898a56de60abd8c1)
Reply
JLCPCBsupport 6 months ago
Hello ; > Can JLCPCB do vias inside pads? Yes we can produce this as long as it much our capabilities : | Features | Capability | Notes | Patterns | | -------- | ---------- | ----- | -------- | | Min. Via hole size | 0.2mm | For Single&Double Layer PCB, the minimum via hole size is 0.3mm;For Multi Layer PCB, the minimum via hole size is 0.2mm | ![](https://jlcpcb.com/client/image/pcbCapabilities/holeSize2.ec579960.jpg) | | Min. Via diameter | 0.45mm | For Single&Double Layer PCB, the minimum Via diameter is 0.6mm;For Multi Layer PCB, the minimum via diameter is 0.45mm. | ![](https://jlcpcb.com/client/image/pcbCapabilities/holeSize3.11b8f399.jpg) | > Will JLCPBB plug the vias or will the solder mask on the opposite side plug the via sufficiently SolderMask will not impact the Via as long as you keep a positive value for the solder mask opening expansion (minimum 0.05mm) | Features | Capabilities | Notes | Patterns | | -------- | ------------ | ----- | -------- | | Solder mask opening/ expansion | 0.05mm | The solder mask should have a minimum of a 0.05 mm "growth/mask opening" around the pad to allow for any mis-registration. | ![](https://jlcpcb.com/client/image/pcbCapabilities/solderMask1.1df74928.jpg) | Note : confirming what Andy said, Blind, buried and capped Vias are not support by JLCPCB.
Reply
tusharpc 1 week ago
thank you this helped me as well. Just pasting a screenshot of my board here incase there are some issues to point out. i have taken care to ensurethe vias and solder mask is within JLC limits. and the pads are of the same net ![image.png](//image.easyeda.com/pullimage/JeA1HwiJRcD1ILGNrILwEA6uyOkiTX97pzSMfuwz.png)
Reply
JLCPCBsupport 1 week ago
@tusharpc you can upload your design files to our JLCPCB ordering webpage and get them to be verified before finishing the payment as it is mentioned in the 10th section of the following guide link : [https://support.jlcpcb.com/article/21-how-do-i-place-an-order](https://support.jlcpcb.com/article/21-how-do-i-place-an-order)
Reply
andyfierman 1 week ago
@tusharpc, Why do you need to put vias in pads here? Normal practice is to track from a pad, insert a vias in the track to change layers then track from the via to the next pad. Inserting vias in pads is generally to be avoided except under extreme situations like the pads under high density BGAs. Other points: 1. You have silkscreen outside the board outline and overlapping in places; 2. You have at least one DRC error;  3. You have two vias between pads that it is unclear whether they are adequatelt tracked to thiose pads; 4. There is probably insufficient clearance between the pads and the board outline on the left and right hand edges of the board;  5. Without sight of your schematic it is not possible to be sure but it looks likely that you have insufficient decoupling capacitors on the device supply rails;  6. Where are the lower pad of C3 and the right hand pad of C9 routed to?
Reply
JLCPCBsupport 1 week ago
@tusharpc you can upload your files to our ordering web page and select the "Review Before Payment" and this way your files get to be checked before you proceed to any payment as it is mentioned in the 10th point of the following guide link : [https://support.jlcpcb.com/article/21-how-do-i-place-an-order#:~:text=You%20can%20also%20directly%20go,PCB%20sizes%20%3C%3D%2010cmx10cm](https://support.jlcpcb.com/article/21-how-do-i-place-an-order#:~:text=You%20can%20also%20directly%20go,PCB%20sizes%20%3C%3D%2010cmx10cm))
Reply
tusharpc 5 days ago
@andyfierman thankyou for your detailed review, I apologize as this was still a work in progress, this is 4 layer board, layer 1 and 4 - signals, layer 2- vcc . (5v & 3.3v ) ; layer 3 - ground copper pour. The majority of the vias in pads are connecting the ground pour or vcc pour to capacitors, ICs. to save space on the board for signal traces ( my board outline is severely limited to this size especially width Other points: 1. You have silkscreen outside the board outline and overlapping in places - the pads on the edges are to be "exposed" for wires to be soldered ( i have done this in the past) 2. You have at least one DRC error - will ignore as this is WIProgress 3. You have two vias between pads that it is unclear whether they are adequately tracked to those pads; also work in progress and they will be connected to adjacent pads - (ground) 4. There is probably insufficient clearance between the pads and the board outline on the left and right hand edges of the board; -same as 1 5. Without sight of your schematic it is not possible to be sure but it looks likely that you have insufficient decoupling capacitors on the device supply rails - agreed, but i have tested in the past and should be sufficient performance wise, also i will be using a buck convertor that has its own decoupling in the pcb 6. Where are the lower pad of C3 and the right hand pad of C9 routed to? - both are ground, both are decouplers, also work in progress. once again thanks for your detailed response. primarily i wanted to be sure JLC can do Via in pad - which seems they can
Reply
andyfierman 5 days ago
@tusharpc, Thanks for taking the time to reply.
Reply
Login or Register to add a comment
goToTop
你现在访问的是EasyEDA海外版,使用建立访问速度更快的国内版 https://lceda.cn(需要重新注册)
如果需要转移工程请在个人中心 - 工程 - 工程高级设置 - 下载工程,下载后在https://lceda.cn/editor 打开保存即可。
有问题联系QQ 3001956291 不再提醒
svg-battery svg-battery-wifi svg-books svg-more svg-paste svg-pencil svg-plant svg-ruler svg-share svg-user svg-logo-cn svg-double-arrow
We use cookies to offer you a better experience. Detailed information on the use of cookies on this website is provided in our Privacy Policy. By using this site, you consent to the use of our cookies.