Your project is public. The ratline is telling you that there are GND nets on one board and GND nets on the other but that they are not connected by copper. There are no ratlines between pins on the two boards because you have given them different net names between the tow places in the schematic. Please read: [https://easyeda.com/forum/topic/Understanding-Ratlines-371bdbf646c54b23a57451eb05b2026d](https://easyeda.com/forum/topic/Understanding-Ratlines-371bdbf646c54b23a57451eb05b2026d)<br> <br> Please note however that you have taken the ability to connect components by netnames rather than just by wires to such an extreme that it is very hard to read your schematic. You have also complicated the schematic by giving some nets two net names as shown by the warnings in Schematic Design Manager. Whilst this practice generates warnings and not errors, it adds to the difficultly in reading your schematic and therefore accurately checking the connectivity. A cursory glance shows that you have made the tracks to the inverting inputs of the TL074 far too long: these nets are highly susceptible to stray pick up and parasitic capacitances. There is no decoupling capacitor near the -12V pin of U4. Check your clearance between the two boards: I'm not sure your headers are tall enough to clear a vertical installation of U5 in a TO-220 package (did you intend this to be a TO-92 package and if so check the power dissipation with 7V across it and whatever your expected load current is through it).

Hey :) I think "very hard to read" should be replaced with "extremely hard". But I'm aware of that haha. \- I will look into the changes you proposed :\) Just to be sure\, the inverting inputs you are talking about are pins 9\,13\, 2 and 6 of the op\-amp ? How long is maximum ? \- Do I need to add two more decoupling capacitors \(see picture below\) ? I already had two \(C39 and C40\)\. The netports are quite confusing\. \- Yes it is a TO\-220 package\.\.\. you're right\, It won't fit with the headers and the PCB supports \(11mm\)\. Do you think I can bend it ? I ordered stackable female pin headers \(do you think it's a solution ? \- I searched online and I found that the Power and ground traces should be wider\. But I didn't find any numbers\. I have 12V 1A power supply with a 5V voltage regulator\. Can you tell me by how much should I widen the trace ? My standard trace is 0\.26 mm\. And thanks again ! That's very kind of you to help me:) 

@andyfierman sorry forgot to mention your name. don't know how to edit my comment.

@Alex293456, No problem. Track width is governed by current through it and the acceptable  temperature rise or voltage drop. There are online tools that will calculate this for you. A good move would be to include a ground plane on one side of each board then you csn route the +/-12V rails but let the ground flood join up the grounds. You may need to do a bit of shuffling or route tweaking to get all the bits of ground plane to join but if you group components carefully to simplify the rats nest before you start routing that will also improve the chances of the ground flood joining up. You may already have enough decoupling caps but they need to be as close as possible to the supply pins. That's one reason why the ground flood is a good idea. The nets around the inverting opamp inputs are called virtual grounds and they too need to be kept to the absolute minimum total track length. Have a look at some of the opamp apps notes from TI, Onsemi and AD

@Alex293456, If your total 5V current is below about 20mA you could probably replace the T0-220 packaged 7805 with a TO-92 packaged part as the dissipation would be (7V*0.02A)W = 140mW which is probably low enough for the device to be freestanding with no extra heatsinking required. Otherwise you can change the footprint to one of the horizontal mount TO-220 versions form the library. There are various available such as these two:  or: 

@andyfierman I have two more questions :) Since this ratline is ground (circled in red), can ignore it ? If every component is connected to ground by the 2 ground planes on each PCB (not drawn yet). And why not putting the ground plane on the entire surface of the PCBs ? 

@andyfierman Thanks for the tip !

@Alex293456, Sorry I should have said to start with that you can ignore that GND ratline. You could put a ground plane over the whole PCB but it depends how you are going to have them made. Are you manually panellising to make a panel with the two boards on then covering both with a single big ground plane might work OK: check JLCPCB Capabilities. If you are simply putting two designs on one board and then splitting them apart using a V-Cut then that works OK because EasyEDA will automatically create boundaries to the copper areas and inset them from the V-cut lines to prevent any exposed bare copper edge along the cuts. Note that V-Cut lines are created simply by adding more Board Outline lines to the Board Outline layer.

Here is a tutorial video on how to make and work with modules in EASYEDA [https://youtu.be/E2dszWjxtAY](https://youtu.be/E2dszWjxtAY)