Please post the link to your public project. A Gerber file is not enough for a diagnosis. Thanks.

@andyfierman The project link is [https://easyeda.com/iamashwin99/rt_probe](https://easyeda.com/iamashwin99/rt_probe) and the pcb that has the problem is PCB\_Multi\_circle Thanks

Btw, you will make the routing much tidier if you rotate items like R7, R8 and R9 by 180 degrees.

@andyfierman Ah! thanks for the tip, ill take care of such things

I don't think this is the problem but you can delete the outer silkscreen outline... 

The gerber file you have uploaded in your link above is not from the EasyEDA PCB that you have linked to. It is either from a different project or has been post processed to produce this:  This looks like you have tried to panellise it. Please do not do this: EasyEDA with JLCPCB has a process for producing panellised boards. There is also a problem with the Gerber file which, if you had checked it using the recommended **gerbv** gerber viewer software, you would have found. In the above screenshot, your .gbl layer is missing from the list. That is because if I try to open it, **gerbv** crashes. You need to tidy up the layout and tracking on your existing single circular PCB and then follow the instructions for how to panellise it: [https://docs.easyeda.com/en/PCB/Panelize/index.html](https://docs.easyeda.com/en/PCB/Panelize/index.html) and see also: **Panelization with space** in: [https://jlcpcb.com/capabilities/Capabilities](https://jlcpcb.com/capabilities/Capabilities)

@iamashwin99, I have searched through all the files in your combined.zip Gerber file archive and cannot find any reference to **CIRCLE_Y9.** Although I have found some issues with your project, I have no idea how they may relate to the audit report you have been sent by JLCPCB. * You might like to contact whoever informed you of the issue or: [https://support.jlcpcb.com/article/45-contact-jlcpcb](https://support.jlcpcb.com/article/45-contact-jlcpcb) to ask them to explain in simple terms what their failure report actually means because at the moment I have no idea how you can be expected to fix the problem that their audit report is referring to from the information that you have been given. * EasyEDA customer users should not be expected to be experts in PCB manufacturing terminology. :)

@andyfierman Thank you so much for your help, I had used the method prescribed in the video [https://www.youtube.com/watch?v=iYrUztOn3dU](https://www.youtube.com/watch?v=iYrUztOn3dU) for paneling. However\, I don't think paneling is not the problem since I have used this method for a different PCB of the same project \(file named PCB\_Multi\_Rect from the mentioned project\) and that got through the audit all good \(Ihave uploaded that Gerber here [https://transferxl.com/04jwrzS774xx0D](https://transferxl.com/04jwrzS774xx0D)). I did contact JLC PCB but got no reply, hence I opened this thread.

@iamashwin99 Dear Sir, This is Eunice Yin from JLCPCB, so sorry for the possible inconvenience caused to your order. The reject information you get from our support team is about the connection between your sub-boards are too small, they may be broken off during production, so we advise you to increase the connection width.