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how to generate pick and place for a full panel at JLCPCB
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nir_be 4 years ago
Hi, I have a ordering  problem at JLCPCB. I want to order panel and assembled it at JLCPCB, bat there are problems. The BOM and  pick and place file that EAsyEDA generate for the panel are for only one board  So JLCPCB don’t want to assemble the full panel because thy don't have the correct coordinate for the full panel components. How can I generate coordinate for all the component in the panel? The second problem that I have  that the panel are not cut correctly, the brake fingers in the middle of the panel are full, so after assembly we wont be able to break them. Please advise ASAP thank you
Comments
Albert Degenaar 4 years ago
Hi,   I am also having the same issue ordering a panelized board for assembly.  Would this be considered a bug? Thanks
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UserSupport 4 years ago
If you using editor panelize tool, it only generate one PCB pick and place file, JLCPCB will accept it. If you want to all panelize borad's pick and place file, you need to panelize the borad manually by copy and paste. via:[https://docs.easyeda.com/en/PCB/Panelize/index.html#Panelize-by-Manually](https://docs.easyeda.com/en/PCB/Panelize/index.html#Panelize-by-Manually)
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wescom 3 years ago
@UserSupport "If you using editor panelize tool, it only generate one PCB pick and place file, JLCPCB will accept it." hi this is not true, BOM and CPL files are not generated correctly when working with the paneling tool. the data contained in the generated files only apply to a single board, not to all of the panel, that can be seen in the gerber viewer when it is quoted, and later when the BOM file is processed, it does not include all the necessary electronic components for all paneling. What would be the solution to this?
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UserSupport 3 years ago
@JLCsupport JLCPCB team please help with this issue
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jbk1 3 years ago
Yes, it would be really great if the BOM and pick and place files could be generated to fully populate a panelized PCB.
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UserSupport 3 years ago
@jbk1 v6.3.53 is released, it supports to export panelized pick and place files, please refresh the page to update.
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jbk1 3 years ago
@UserSupport That's fantastic, and great timing :) Many thanks for providing a great service.
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jbk1 3 years ago
Looks like there may still be a few problems to work out with the panelizing support! All the parts seem to have a constant xy offset from their correct positions. ![Selection_097.png](//image.easyeda.com/pullimage/OPhGzpSdVfGYZzRFsDkNWqHx9jz8a2qMOTJ204KX.png)
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UserSupport 3 years ago
@jbk1 we tranfered this issue to JLCPCB, they will take a look
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jbk1 3 years ago
@UserSupport Thank you. It's not urgent, my first order will just be for non-panelized boards anyway. I was just curious to see how this worked.
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wescom 3 years ago
@UserSupport hello do you have any news regarding this topic
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wescom 3 years ago
apparently the files are well generated by easyeda, the problem (I think) is in the JLC viewer of the pcb with the components to mount. sorry my writing i don't speak english
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JLCPCBsupport 3 years ago
@wescom hello ; > @UserSupport hello do you have any news regarding this topic Well, it says that the release of the new version v6.3.53 provides a P&P files for the panelized design, since the P&P is well generated then there will be no problems regarding the SMT assembly at JLC because our assembly process will exactly follow the coordinates generated through the P&P files. Despite all this, I will investigate more with the JLC technical team, if you have any issue with your design or order you can send me your order number and we will double check the P&P files and let you know the results.
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Mr_HaleYa 3 years ago
![image.png](//image.easyeda.com/pullimage/mS8n5MmtOoQgCcSxmRXEHZLiFAqHFFssnNW71kw5.png) I am having the same problem. Wescom says that It is just the JLC viewer that is doing this but the actual file is correct so assembly should work???
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JLCPCBsupport 3 years ago
@Mr_HaleYa Hello YES exactly, just our viewer issue, so all what I advise you to do is to check your files in any external DFM analyzer and if the result is good then the assembly will be correct in JLCPCB :)
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wescom 3 years ago
@JLCPCBsupport del mismo  modo cuando se sube el archivo gerber (panelizado por easyeda), el visor aparentemente falla ![Captura.JPG](//image.easyeda.com/pullimage/9Ta5MIpVF6txVzDQFn6mX9N0lR7uL4ICPAcxl14s.jpeg)
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wescom 3 years ago
@wescom when uploading the gerber file (paneled by easyeda), the viewer apparently fails
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JLCPCBsupport 3 years ago
@wescom Hello Once you chose to create your Panel by EasyEDA then it will be not visible in our Viewer (same for assembly) so it shows only the first position of the Panel, but producing this panel will not show any problem. This happen only when you make your Panel automatically generated by EasyEDA, if you create your panel design manually than you will visualize it in JLCPCB viewer.
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