Hi LISA_DALTON This issue is because of we in order to support multiple netlabels on one wire,  so the when converting to PCB , the editor will using one netlabel to be the PCB net, if you don't want to route them again, you just need to route what you want to add, and ignore the ratlines. we are working on it , it will be fixed at the future version. thank you

@Tutorials I have ignored the ratlines, and as I have said, on the Gerber, the traces routed correctly in PCB Editor don't show on the PCB. It would seem I am stuck. All the the net names are even the same in the trace that won't show on the PCB. The via's the pads, the trace are all named L9_2. I would like to add that the new software minus the bugs, is noticeably better.

@LISA_DALTON Yes， we already added it to the BUG list. waiting for the fix.

@Tutorials Is their some one who can help complete this ONE trace so that I can complete my PCB and place my order? -Lisa D

Hi Lisa, can you give me the URL of the schematic and PCB so I can have a look?

Sorry Lisa, My bad: you've already posted the link. I missed it on my phone screen.

Hi Lisa, Had a look. I think the the ratline between R5 and L9 is because you have placed a via or pad in the middle of a single layer pad for one end of each of these devices and one of these vias is not connected by a discrete piece of track. In general for PCB design it is not good practice to put vias in the middle of pads unless they are specifically intended for things like heatsinking and low impedance, high current paths and even then subject to certain rules and cautions. This is something that even the manufacturers of devices with central ground and/or heatsink pads do not describe well in their datasheets and apps notes. One reason is that the via can suck solder down the hole away from the pad so the SM device ends up without enough solder to form a relaible joint. With two terminal devices especially, if there's a via at one pad and not the other the difference in the surface tension between the solder remaining at each of the device contacts can offset the position of the device or even result in so-called "tombstoning" where the chip ends up stood on one end. If you're hand soldering in small batches then you will probably be OK but if you're using a stencil and solder paste then this could be an issue. That aside, your PCB shows DRC errors so you should be OK to ignore it but if are seeing a problem in the Gerbers then you can fix the connectivity (and remove the ratline) by this process: 1\. move the via on the right hand end of L9 to the right\. This will drag the track on the bottom layer\. Note that there is no track between the via and this pad of L9; 2\. Add a short track \(0\.8mm width or so\) from the pad to the via\. The ratline should now disappear; 3\. Move the via back into the oroginal location\. This will drag the track on the bottom layer but it will now have a small kink in it as it resets itself to a 45degree angle by adding a \(green\) vertex; 4\. locate and delete the extra \(green\) vertex\. This will remove the kink\. If you move the via in the left hand pad of R5, you'll see that it is already connected to the pad of R5 by a discrete track. Two other observations: A. There is no 100nF or so 400V X capacitor across pins 3 and 4 of L1. This means that there is no lowpass filtering action operating forany possible differential mode noise being exported by the input side of U2 back out toward the mains supply. B. The AC ground is being used as the low voltage side ground. This may be something that it mandated by your Design Requirements Specification but if not you may want to consider splitting the grounds into the AC chassis ground for the input supply filtering and split X cap grounds and having the isolated low voltage side on a separate low voltage ground. You'd have one small ground flood for the chassis ground on the left hand side of the PCB and another on most of the right hand side for the supply ground. That then prevents any noise that you're trying to route into the chassis ground from having a direct path to couple straight into the isolated supply ground and vice versa.

@andyfierman Hey Andy, Thanks for responding, I have no-one here to bounce my work off of most of the time so your suggestions are VERY much appreciated. That said, I believe I actually have those 2 bases covered you have mentioned. In the schematic, C1 is across Line to neutral for my X-cap. Also though it doesn't show, I had planned on doing 2 separate floods, as what is in the attached JPG. Is this basically what you meant? I just had the full flood to check the components that should be grounded were indeed grounded. That will be my last step. This is why the only GND connection is by the AC input. This JPG is a gross example, but I think you get the point.I also have C2 and C3 as split caps across Line to Neutral, with the center going to GND. You are to good to miss that, so are you speaking of something else? In the past I have not had the tomb stoning issue, mainly because the vias were smaller, and were filled with the green solder mask, so no solder could flow through. In the PS areas, I am looking for the low impedance connections to ground for noise issues, and simplicity. But your point is well taken. Do you work for EDA, or just a glutton for punishment/ very helpful person? Either way, I for one want you to bear my children at this point. ; )   Yes I have a strange sense of humor. We do have Techs here, but not qualified to talk about the points you have been bringing up. Mainly they are here for assembly, and the lower level trouble -shooting. Training them is another of my varied responsibility's. I have spent allot of time at at steel rolling mill plant designing and implementing instrumentation. But this board is now all my responsibility, and constantly being pulled away means I will miss things. So your input is gold. Thanks again, I'm going to give your fix on that trace a shot. (The program bugs have really slowed me down as well.) -Lisa D

OK Andy, I see why you missed the X-Y caps. If you see the schematic they are obvious. They are placed where they are because in the AC-12Vdc switcher (CUI model [PBO-5 Series Datasheet)](https://www.cui.com/product/resource/digikeypdf/pbo-5.pdf) That's how they have it layed out to meet FCC Consumer Electronic EMI Specs. This board, and the main Logic board to follow, are both going to end up in production, So I am actively working on making both boards compliant in all ways. -Lisa

Hi Lisa, These two screenshots should show what I mean about having electrically separate CHASSIS and GND planes.   I have hacked your schematic and PCB layout to add CHASSIS ground and the missing low pass filtering cap. I haven't created copies of these hacked files because I think there's another bug lurking after the update and I (a) haven't had time to investigate and file a bug report and (b) I don't want to give you what might be a broken file. The only caution with these two planes is that the twi traces going to pins 1 and 3 of U2 have to cross the plane break. It's too complex to explain here but the recommended way to cross a plane break is (i) don't and (ii) if you cannot avoid it, treat the two traces as a closely coupled differential pair and route them as close together as their voltage rating clearance will allow and cross the plane gap at right angles to it. This minimises the area enclosed by the traces and the edges of the planes to minimise any possible EMI from the signals crossing the gap. The planes can be close together since they do not need the same high voltage clearance as between the mains traces (but beware clearances between pins at mains voltages and the planes around them). Some other points I've noticed: 1\. U3 and U4 seems to have some text that is on the bottom copper layer\. I'm guessing that's a petit bijou errorette in the PCB footprint and that's why you've placed the text itself off\-board\. 2\. Although the PCB file seems to have no errors\, the schematic does:  It might be worth checking that everything really is connected in the schematic (set the grid and the grid snap to 5 and nudge all the joins to make sure everything that should be joined snaps into the same places). BTW, here's a link to some notes by the man who knows about crossing gaps, Dr Howard Johnson: [http://www.sigcon.com/Pubs/edn/diffuturn.htm](http://www.sigcon.com/Pubs/edn/diffuturn.htm) I was lucky enough a few years ago to be able to go to a solid week of his courses on Black Magic (High Speed Signal Design) and Advanced Black Magic (High Speed Signal Propagation) plus at other times, courses by the very wonderful Doug Smith, Rick Hartley and Bruce Archambeault. I kind of loosely work part-time for EasyEDA: [https://easyeda.com/page/about](https://easyeda.com/page/about) (it's a shame they've cropped the photo because it used to show my "Resistance isn't futile: it's voltage divided by current." T shirt. The rest of the photo is real though: you can't photoshop out that much wear and tear...) part time for me: signality.co.uk (plug, plug, plug!) and part time for another company.

Here's a schematic (for an active power factor controller) showing a similar input filtering and grounding arrangement to what I'm describing: [https://www.arrow.com/en/reference-designs/53w-410v-ac-to-dc-single-output-power-supply/47e3f9a949b7fd42c98edb976f3f5e8b](https://www.arrow.com/en/reference-designs/53w-410v-ac-to-dc-single-output-power-supply/47e3f9a949b7fd42c98edb976f3f5e8b)

I should add that there's nothing wrong with the way you have arranged the grounding where you have the input filter and the supply side on the same ground, just joined at one point where the AC supply ground comes onto the board. It avoids having to cross a plane break (as long as the only traces that go over the 'bridge' copper between the two areas are the two high voltage traces to pins 1 dn 3 of U2 and no other traces cross over the gap between the two areas) but it does mean that the PSU outputs are all connected directly to the mains earth which could give problems with a ground loop if you connect the supplies to some other circuit that is also connected back to the mains earth, say through the PCB mountings to an earthed box. Having a separate Chassis and Supply GND can avoid this problem. If you go fo a separate chassis and supply GND then you may want to disconnect the PCB from supply GND and connect one or more to the chassis ground, again to avoid creating an accidental ground loop somewhere downstream. Getting grounding right for EMC is always a tricky problem because it is very applications dependent. Sections 3.11 - 3.13 of: [http://www.compliance-club.com/archive/keitharmstrong/design_techniques3.html](http://www.compliance-club.com/archive/keitharmstrong/design_techniques3.html) are particularly helpful.