DRC Clearance problem EasyEDA V6.1.52 Build Date :07/01/2019
posted by jackberg2012 , 2 days ago.
replied by jackberg2012 , 1 day ago.
Solid region with exposed copper cannot be deleted
posted by amsgomes_9956 , 3 days ago.
replied by amsgomes_9956 , 3 days ago.
Sanity check my first PCB design?
posted by Gregg Reno , 5 days ago.
replied by Gregg Reno , 4 days ago.
How can I update the names of electronic parts
posted by FERASALNWELATI , 6 days ago.
replied by andyfierman , 4 days ago.
DRC Errors in my simple PCB Layout
posted by Stefan Draeger , 9 months ago.
replied by andyfierman , 1 week ago.
как отзеркалить модуль на печатной плате (перенести на другую сторону- снизу - вверх)
posted by Александр Захаров , 1 week ago.
replied by Александр Захаров , 1 week ago.
does not work refresh copper area
posted by romiksm , 1 week ago.
replied by UserSupport , 1 week ago.
How do I tent my vias on pcb layout?
posted by aaronyong , 2 weeks ago.
replied by UserSupport , 2 weeks ago.
От чего много ошибок ? Проверил 5 трасс , проблем не обнаружил
posted by Artos5 , 2 weeks ago.
replied by UserSupport , 2 weeks ago.
How to customize paste mask layer to prevent stencil from having holes for jumper pads
posted by John Kougoulos , 1 year ago.
replied by rom1nux , 2 weeks ago.
Do not want Top layer track to connect through the Component top layer pad
posted by karansoi , 2 weeks ago.
replied by andyfierman , 2 weeks ago.
【Forecast】3D model preview is coming soon
posted by UserSupport , 1 month ago.
replied by neutronstriker , 2 weeks ago.
