Have you run the Gerbers and check them to see if the vias have actually been placed?

They have not, no. No DRC errors or other errors, although the default size of the vias is at the minimum for the default DRC rule. I bumped the size up a bit just in case, but it didn't help. (I exported Gerbers and looked at them with gerbview) Thanks!

I'll make the project public and post a path to this thread in a few minutes.

Here's the project path: [https://easyeda.com/audiomath/yr-controller](https://easyeda.com/audiomath/yr-controller) Thanks!

My first question is why on earth are you spending all that extra money on a 4 layer PCB when you have entirely through hole components, only one chip or module supplied from 3.3V and only 2 traces on the bottom layer which could easily be routed onto the top layer? Like this:  You could do the whole board on 2 layers and still have a complete ground plane on the bottom with a large area of 3.3V on the top. Beter still swap all your traces and a 3.3V copper area onto the bottom layer and put a GND copper area on the top layer so when you accidentally short a pin to the plane a when you are debuggin the first board you have a short to GND - which most devices will survive - rather than a short to 3,3V or 24V, which they may not. Also, if you only want 250mA at 3.3V why not put a single stage 24V to 3.3V output buck converter or buck converter module on the board instead of buying a 3A step down converter module, setting it to 5V and then linearly regulating down from there to 3.3V? If the switcher output has a bit too much ripple on it then at 250mA a simple LC filter on the regulated output would be all you'd need. If you insist on using 4 layers then set the inner two to PLANE and not SIGNAL and then assign the planes to GND and 3.3V as required. Oh, and add a proper netlabel to the +3.3V net so the plane assignment actually works properly.  

Ok, it's a prototype and I was lazy. The reason for a 4-layer board was simply as an experiment in reducing EMI from the MCU module. There are reasons not to embed signal, which I admit makes the whole thing look strange. The original design is 2 layers, as you suggested. It makes more RF noise than I like. A buck converter wouldn't be used at all if a real design ever came of it - the USB port on the Teensy MCU module supplies 5V to an onboard 3.3V regulator. I have boxes (literally) of these parts. All points acknowledged, but I'm left with my original question. Given your response, If I changed the inner two layers to planes, would the via generator work? (rhetorical, I'll try it) Thanks!

If you have problems with EMC then you should consider using additional filtering on the i/o lines of the board. This could range from simple RC low pass filtering to T LC filters from the likes of Murata. You also need to tighten up the layout. The components are unnecessarily spread out and so there are too many long loops of track. Also, adding an SMPS module based on a simple buck mode topology which chops the input current, with no input or output side common or normal mode chokes to an experimental board which you are trying to quieten down is arguably less than helpful. No amount of adding layers will correct for poor layout and attention to the filtering of interfaces. I assume that you are driving a couple of 24V motors so also note that your choice of - or connection scheme for - the mosfets is wrong. You either need to use p channel mosfets or to rearrange the n channel parts to have their sources grounded and the motor connected as a load from drain to the 24V rail with the flyback diodes appropriately reconnected. I would also question the need for both silicon and schottky diodes in parallel for this function. Your placement of 10nF caps on the outputs of the processor driving the npn transistor gate drivers is questionable since although it slows the signal transition and filters noise to ground, it also causes large switching current spikes from the processor supply on rising edges and through the ground return path on falling edges. With the very long tracks to these drivers that is an interesting potential of EMC, signal and power integrity problems. Slowing down edges to mosfet switches can also lead to power dissipation problem in them if the transitions are too slow. Such issues can easily be checked in simulation.

FWIW, the switches are independent P-channel, the motor has two windings.

"...the switches are independent P-channel..." They are given as Fairchild FQP50N06 in your schematic:  The symbol is for an N channel part which is what the FQP50N06 parts are: [https://lcsc\.com/product\-detail/MOSFET\_ON\-Semiconductor\-FQP50N06\_C2710\.html](https://lcsc.com/product-detail/MOSFET_ON-Semiconductor-FQP50N06_C2710.html) [https://datasheet\.lcsc\.com/szlcsc/1809111813\_ON\-Semiconductor\-FQP50N06\_C2710\.pdf](https://datasheet.lcsc.com/szlcsc/1809111813_ON-Semiconductor-FQP50N06_C2710.pdf) Something similar to this is what you should be using here: [https://www.onsemi.com/pub/Collateral/FQP47P06-D.pdf](https://www.onsemi.com/pub/Collateral/FQP47P06-D.pdf) but which sadly are zero stock at LCSC: [https://lcsc\.com/product\-detail/MOSFET\_ON\-Semiconductor\-FQP47P06\_C462765\.html](https://lcsc.com/product-detail/MOSFET_ON-Semiconductor-FQP47P06_C462765.html)

Are the motor windings commoned and connected to case ground? If not then it would it not be cheaper to use 2 N channel MOSFETs as low side switches with the motor windings commoned on the high side?

Yes the motor windings are commoned. That common floats in the system, but it doesn't hurt to tie it to ground. I have lots of IRF9540. Far too many, in fact. :-) Thanks!

The end of this Bug Report seems to have got to the bottom of the missing bias problem and offers a workaround: [https://easyeda.com/forum/topic/Copper-Area-Add-Rmove-Vias-not-working-or-feature-not-clear-ff0ea29cb3ff4fac8be76b56e7bf9a37](https://easyeda.com/forum/topic/Copper-Area-Add-Rmove-Vias-not-working-or-feature-not-clear-ff0ea29cb3ff4fac8be76b56e7bf9a37)

Thanks, Andy.