I think this is a good rule

This feature could be extended to help in the design of controlled impedance traces. It works like this: If the PCB stackup is known (number of layers, layer spacings and dielectric constant for the insulating layers) then the trace width can be defined in terms of a desired trace impedance on a given layer (i.e. if it is microstrip, stripline etc.). To do this will require: 1. high quality information about the PCB stackup; 2. a high quality calculation of trace width based on the desired impedance, the PCB stackup information and which layer the trace is to be placed on. By `high quality calculation` I mean using a 2D or 2.5D field solver, not a simple formula based calculator. A couple of suitable FOSS field solver tools are: http://mdtlc.sourceforge.net/ (I have used mdtlc sucessfully a couple of times) https://sourceforge.net/projects/mmtl/files/tnt/1.2.2/ (I have not used this) It would be nice one of these could be integrated into EasyEDA at some time in the future.

Well I have found meanwhile that in autorouter you can define special nets and set them to a particular width, so in some sense the feature is already available, sorry I am a newbie :) Maybe just a thought if it is useful to link special nets also to wires in schematics.

Fededim, No problem. It's a good suggestion and it prompts some further ideas. For example, one of the features that EasyEDA does not yet support is what are called `Net Classes`. This is where a class of nets can be defined to have certain parameters such as width and/or clearance. For example, a `Mains` class could be defined to have a width of 5mm and a clearance of 3mm whilst a `Signal` class could have width of 0.25mm and a clearance of 0.2mm. If net classes can be supported then this information can be attached to a net in the schematic and it will then automatically be assigned during the PCB layout.

Well that would be the best way

net classes will be provided, We will spend time to develop a new version of EasyEDA.