Hi Tommy, What you are reporting is not a bug. It is normal, expected behaviour for complex simulations. Getting a simulation to run in all possible conditions is not a simple task to accomplish. When you say things like: `Schematic "Test 5" aborts simulation, though it had already worked correctly and given desired results.` that is not actually true. For example, there are differences between your simulation schematic in Test 4 and Test 5 that are quite enough to cause a simulation that works in Test 4 to fail in Test 5. Your circuit is too complex to go into and debug verything that *could* be causing convergence failures to occur but I will list a few of the possible causes and then make a simple suggestion that seems to make your simulations much more robust. 1. Any two of Current Sources `US`, `VS` and `WS` are effectively series connected. It is not possible to connect ideal current sources in series. The only reason this works at all in your simulation is because you have carefully defined the signals such that the sum of the sources at net `WS is always zero, except of course that any tiny numerical error or rounding offset could cause that to no longer hold in which case the residual current can cause a numerically huge voltage to appear at net `WS`; 2. Net `WS` has no DC path to ground. Having a current source with an infinite resistance across it allows numerically 'infinite' voltages to be developed across the source; 3. You have resistances of only 5 uOhms in the same circuit as having very high resistances - in the order of 1 GOhms - represented by the reverse resistance of diodes. This is a classic situation for convergence failures to occur because you have a ratio of around 1e15 between the largest and smallest currents and voltages that the simulator has to deal with; 4. Several of the B sources implement switched functions based on IF, THEN, ELSE type structures. These are another classic source of convergence failure bcause they represent effectively instantaneous transitions requiring infinitely small timesteps to resolve. ##### Fortunately in your simulations, there is a simple modification that should get most of them running in a much more well behaved manner. Simply insert the following line as a spice directive: `.options RSHUNT = 1e12` This is explained in the ngspice manual: http://ngspice.sourceforge.net/docs/ngspice-manual.pdf#subsection.15.1.1 and section 15.1.2.1 in: http://ngspice.sourceforge.net/docs/ngspice-manual.pdf#subsection.15.1.2 * For more about how to get simulations running well in EasyEDA, please read: https://docs.google.com/document/u/1/d/1OWZVVFRAe_2NW3WratpkA_SGuHa5AcRow5ZRfvcoVTU/pub * For more background about convergence failures and how to avoid them, I can recommend reading: **Chapter 8: Convergence, Accuracy and Performance** in: http://www.simetrix.co.uk/Files/manuals/8.0/SimulatorReference.pdf and: http://www.intusoft.com/articles/converg.pdf