I'll explain in more detail later but try replacing C1 with an normal 100uF cap and adding a netlabel called `RC` to the junction of C1 and R2 and then insert this spice directive: `.ic V(RC)=0` Also reduce the max step size from 100m to 20m so the tran statement is: `tran 20m 100` I don't know why the pulse output hops between two different high levels.... Tricky stuff spice. :)

@andyfierman Well, that is an improvement: ![enter image description here][1] Is it possible there's a problem in the implementation (which I assume is declarative) of the 555 I'm using (which was taken from the EasyEDA Lib). Maybe there's a better/different 555 that would produce correct results (i.e. a clean square wave)? [1]: /editor/20160601/574e3c6848e6f.png

I'll get back to you onn that one. How accurately do you want to model a 555 and which particular (bipolar or CMOS) version?

### Some thoughts about why the output is a bit irregular. SPICE works by making estimates of where a signal is, where it is going and how fast it is changing. One of the contributions to how spice adjusts these estimates is based on the derivatives of signals so calculations in spice tend to be concentrated around fast rates of change such as fast transitions and turning points around things like sawtooth oscillators etc. Some spice engines are better than others at getting this right in long simulations with large permissible maximum time steps. SIMetrix and LTspice are excellent but even though LTspice is free, both are proprietary versions of the original Berkeley spice. Ngspice is free as in FOSS but is not quite as good at getting the balance right between long simulations and large timesteps. Basically, if you use smaller maximum time steps compared to simulation time then the simulation will tend to be more accurate but of course will take longer and generate more data. EasyEDA has some limits on the maximum size of simulations and simulation data generated simply to limit the server usage and bandwidth. It also reduces the effect of anyone trying to deny access to EasyEDA by delibrately launching lots of huge simulations. When running a simulation via the Green Man `Simulate...` button, the limit of the ratio of stop time to timestep is 1000:1 but if a simulation is run using a spice directive placed directly in the schematic then - depending on the amount of data produced by the simulation - this can be increased to about 10000:1. One way round this is to use the option to only display the results from towards the end of the simulation by specifying a `Start time`. ### How short does the maximum timestep need to be? Sampling rates such as used in Digital Scopes suggests using time steps at least 10 times shorter than the fastest signal in your simulation. For example, the slew rate of the LM741 is only about 1V/us and it is slewing several volts, so this would suggest that edges are quite slow; in times of us. However, internally to the opamp model there may be signals, particularly currents, that are changing much faster. Hence a much shorter time step would seem to be required. Choosing a timestep of about 1/(10*GBW) where GBW is the opamp gain bandwidth product (about 10^6 for the LM741) is probably a better starting point for opamp based switching circuits. However, this significantly - and unnecessarily - increases simulation times and the amount of data generated by a simulation because spice is more adaptive in the way it chooses the points that it calculates the waveforms for. Sometimes it makes mistakes which is where odd behaviour starts to appear in simulations and in the extreme case, simulations suffer convergence problems and fail to run or just generate rubbish. Unfortunately the humble sawtooth generator - in almost any form - is actually one of the most difficult simulations for spice to get right! ### Why did replacing the A model capacitor with a simple C model and using the `.ic V(RC)=0` ### spice directive make the sim run better? To be honest I don't know exactly. `A` model parts are part of the XSPICE extension to spice. They sometimes help - most of the EasyEDA logic device models are built using XSPICE devices - but not always. Simulation is never perfect and should never be used without sanity checking the results. A lot of SPICE is about learning how to get the best out of the simulation engine and there are always little tricks and tips that need to be tried, even if just to sanity check the results (because SPICE can make a mistake in estimating where signals are heading and generate some very convincing looking total nonesense!). I have around 20 years experience of using spice for modelling and simulation so I'm quite new to the game and I still get stopped in my tracks by some of the things that can make a seeming ordinary simulation go of the rails. So don't be afraid to post to the forum with any questions about getting your sims to work! :)

@andyfierman Very interesting. I recall doing simulations to solve differential equations back in college (applied math major), so I get what you mean when you say that a simulation can go "off the rails." As far as the 555 simulation goes, no, I don't need anything more accurate than what I have now. I was just curious why the simulation of your LM324 circuit produces perfect square waves and the simulation of the 555 does not.