**BUG** Concise problem statement: I have tried to change the parameters of the ADC and DAC bridges used in this example: https://easyeda.com/file_view_How-to-use-logic-gates-via-Xspice_GSM4mEWew.htm so that I can post an example of how the logic family of Xspice logic gates can be changed. The example I am working on allows me to enter a spice .model directive but does not correctly parse the new bridge. I understand what the error report is telling me but I do not understand what I am doing wrong in the schematic to cause the error. Steps to reproduce bug: 1. Run sim 2. Read simulation report Results: Sim report shows error: Missing [, an array connection was expected. Returning . . .Error on line 5 : abridge3 abridge2_2 vol3 dac_bridge2 Missing [, an array connection was expected First few lines of netlist looks like this: ABRIDGE5 [ABRIDGE5_1] [VOL2] DAC_BRIDGE ABRIDGE4 [ABRIDGE4_1] [VOL1] DAC_BRIDGE ABRIDGE3 ABRIDGE2_2 VOL3 DAC_BRIDGE2 ABRIDGE2 [ABRIDGE2_1] [ABRIDGE2_2] ADC_BRIDGE ABRIDGE1 [V1_1] [A1_1] ADC_BRIDGE Error refers to missing square brackets in ABRIDGE3 Expected results: Line for ABRIDGE3 should look like this: ABRIDGE3 [ABRIDGE2_2] [VOL3] DAC_BRIDGE2 Url: https://easyeda.com/file_view_Xspice-logic-gates_NcI0icuM4.htm Browser:Mozilla/5.0 (X11; Linux x86_64) AppleWebKit/537.36 (KHTML, like Gecko) Ubuntu Chromium/30.0.1599.114 Chrome/30.0.1599.114 Safari/537.36