The problem is that you have created a schematic, converted it to PCB but then you are making changes to the PCB  so that it no matches the netlist including the package information from the schematic. The EasyEDA Design Flow is that the schematic is the master document and that any changes are made to that and then the PCB is updated either from Update PCB... in the Schematic Editor or Import Changes... in the PCB Editor. Any changes of the type you are describing will be overwritten by these actions unless you make the same net and package changes to the schematic, which is where they should have been made in the first instance and not in the PCB. Following the Design Flow  means that changes made in the schematic are passed into the PCB with changes to the connectivity made and old footprints removed and replaced by new ones automatically so all you have to do is adjust the footprint position and tracking. To help understand the importance of this aspect of the Design Flow please read (2.2) and (4) in: [https://easyeda\.com/andyfierman/Welcome\_to\_EasyEDA\-31e1288f882e49e582699b8eb7fe9b1f](https://easyeda.com/andyfierman/Welcome_to_EasyEDA-31e1288f882e49e582699b8eb7fe9b1f)

Thanks Andyfireman for the information.