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Hi, First of all, thank you for your quick answer. As I said in my first message, I spent a lot of time on the subject. I came across several links that seemed interesting. The first one suggested lowering the clearance. I did it and I went to the minimum but it doesn't solve my mistakes (0.05mm). The second link suggested that the pads of my nets did not have the same name, which is not the case since I used a schematic. In addition, I also tried to change the position of the components that cause this error, and I even went so far as to change the footprint of the component, but I didn't succeed. I'm putting the project in public for a while. [https://easyeda.com/nicodu95drap/test](https://easyeda.com/nicodu95drap/test)

Four of the DRC clearance errors are telling you that there is a pad overlapping a solid region. Two are the pads for pins 1 and 2 of the 2.4GHz antenna. The other two are the pads for pins 1 and 2 of the NFC antenna. I do not know of any way to make things like inductors and PCB inductors without generating this type of DRC error. For this type of footprint however, these errors can safely be ignored. The other clearance errors are warning that you have overlapped a multi-layer (though-hole-plated or PTH, pad) over a hole. You can place a hole or you can place a PTH multi-layer pad. It makes no sense and there is no need to place both together. You can place a multi-layer pad and select it to be  none-through-plated (NPTH) like this: 

Not commenting on the DRC errors but note that you should not overlap the antenna over tracks on the other layer.  A spacing of 5 to 10mm is the minimum usual recommendation

Thank you very much for your help, I will apply all the advice you have given me!