Hi, I am getting clearance error when I run DRC check on my layout. The clearance limit on DRC settings window is set to 0.152 mm and my copper pour has clearnace setting of 0.254. There are no net around my M3 mounting hole still this error appears. I have 6 such holes on my board and all are giving errors. None of the holes have tracks or any other component interfering within the defined limits. Not sure exactly why this error appears.
![DRCError.png](//image.easyeda.com/pullimage/vKn6Qumj8mQ1MBkJ5JxpwkPQazuRqtSDNqx4kZhp.png)
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EasyEDA
6.1.51