Clearance issue (or bug) ?
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Paolo35 1 week ago
Hello, i need support, when i perform DRC check on pcb  i have two same advice like : “The clearance between two object is less than the Design Rule Checking (DRC) clearance which has different nets.” The eda seem to see a pad that do not exixst and the tracks width is 0.25mm . I’m ready to place a order but i want to be sure thet there are no problem of anything type. Please see also the attached image.Thank you. ![2.jpg](//image.easyeda.com/pullimage/Gp1PBKqozhd5EMnDVbZI9dbFyOwSnqdU7poayLdC.jpeg)![3.jpg](//image.easyeda.com/pullimage/DKjHpJg3k4K4ywFNC3BV5aijZz0UHMCJ8US4YsTg.jpeg) Paul ![1.jpg](//image.easyeda.com/pullimage/KMFLPg47ZrAs8ww1MTMwjOp8YdPAtxY1RVtcIqFF.jpeg)
Comments
andyfierman 1 week ago
Sorry but your screenshots do not give enough information. Please make your Project public and share the Project url.
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Paolo35 1 week ago
Sorry andyfierman but i can't  make public. Not for now, but what the information you need? The DRC see a pad thet not exist in the PCB. I don't know why but some day ago there are two but i have deleted them. Evidently something are still in memory of the project. But what?
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andyfierman 1 week ago
Can you share it privately?
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Paolo35 1 week ago
Yes tell me how . Thanks.
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andyfierman 1 week ago
[https://docs.easyeda.com/en/Introduction/Project-Member/index.html](https://docs.easyeda.com/en/Introduction/Project-Member/index.html) support @ easyeda.com or \@easyeda.com
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andyfierman 1 week ago
Oh.... Hate the way the parsing messes up formatting. That should have said: `or``my_username @ easyeda.com`
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andyfierman 1 week ago
Even that's not quite right but maybe you get the idea? :)
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Paolo35 1 week ago
ok andyfierman, say to me if you can see the project. Thank you
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andyfierman 1 week ago
@Paolo35, I can see it thanks.
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andyfierman 1 week ago
@Paolo35, I am not sure what the problem is but it is related to the two solid regions that you have placed on the toip and bottom layers that go round the outside edges of the board from the lower mid left, clockwise to the lower mid right. If you delete both of them the DRC errors disappear. I notice that you have made almost everything on the board have the same net name of S$200. There is nothing really wrong with this in a board like yours but as is a trifilar winding if you at least name the nets so that there are S$200, S$201 and S$202 and also to rename some of the solid regions that are not electrically connected to each other on the board then this might help you to identify more clearly where the DRC error is coming from. You could also try replacing the two outer solid regions with tracks to see if this clears the DRC errors.
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Paolo35 1 week ago
@andyfierman you are right, the problem has been solved removing and replacing the border that for some unknown reason they don't gave no more errors again. Thank you!
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Paolo35 1 week ago
@andyfierman you are right, the problem has been solved removing and replacing the border that for some unknown reason they don't gave no more errors again. Thank you!
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