Forum - EasyEDA - An Easier Electronic Circuit Design Experience

Latest Topics Latest Replies EasyEDA Std EasyEDA Pro JLCPCB LCSC OSHWLAB General Discuss

Schematic PCB Simulation Skill Extension Feature Requests Bug Reports

Connecting nets through via without merging

908 9

Lorenzo Micheletti 2 years ago

Hello everyone, i am trying to connect two different ground planes through some vias without merging the nets (see Image 2, only the top layer PGND should connect to the AGND). I have tried to use overlapping copper areas like suggested in here (without success): [https://easyeda\.com/forum/topic/Join\_two\_copper\_pours\_on\_different\_nets\-YQKDxP7pH](https://easyeda.com/forum/topic/Join_two_copper_pours_on_different_nets-YQKDxP7pH) Is there any way to do this? I am still a novice with Easyeda, so i am sorry if this is a stupid question! Thank you in advance. Image 1: ![vias.png](//image.easyeda.com/pullimage/SGBGKFmx6sUIOs5soteH69HvY1KMXaa6BEgeWs7D.png) Image 2: ![image](https://www.apogeeweb.net/upload/image/20190220/6368627331019125002602461.png)

Chrome 94.0.4606.81 Windows 10 EasyEDA 6.4.25

Comments

andyfierman 2 years ago

If two copper elements are connected by copper they are by definition, the same net. Therefore they must have the same net name. You can put multiple net names on a net in the schematic but only one name will be implemented in the netlist and therefore on the PCB. Until a "Net-tie" is implemented in EasyEDA there is no solution. See: [https://easyeda.com/forum/topic/Net-tie-a-copper-only-component-with-2-pads-to-split-nets-without-DRC-errors-and-multiple-netname-warnings-b6a099bf01bb4055b821ab398ee37b60](https://easyeda.com/forum/topic/Net-tie-a-copper-only-component-with-2-pads-to-split-nets-without-DRC-errors-and-multiple-netname-warnings-b6a099bf01bb4055b821ab398ee37b60)

Chrome 94.0.4606.61 AndroidOS 10 EasyEDA 6.4.25

Lorenzo Micheletti 2 years ago

I see, thank you!

Chrome 94.0.4606.81 Windows 10 EasyEDA 6.4.25

Lorenzo Micheletti 2 years ago

Hello, sorry to bother you again! Would something like this work? Link: [https://oshwlab.com/lorenzo.micheletti/test-join-nets](https://oshwlab.com/lorenzo.micheletti/test-join-nets) It looks like that the outcome is like in the Image 2 (layer "Inner1" is AGND, Bottom and "Inner2" layers are PGND) of the original post, but i'm not sure that would work on the final PCB. The custom footprint is just two overlapping pads with no paste mask and covered by the solder mask, the bigger pad is PGND and the inner smaller pad is AGND. What i'm unsure of is how in the production those pads are processed: is there a "physical barrier" between the overlapping pads? from the preview it looks like they are correctly merged. Thanks again for your help!

Chrome 94.0.4606.81 Windows 10 EasyEDA 6.4.25

andyfierman 2 years ago

Sorry but this only "works" if you ignore all the DRC errors. Ignoring DRC errors is OK as long as you can be absolutely sure that it is safe to do so. That's easy to do on a nice simple example but is much harder in a real PCB. I've lost track of the number of times this question has come up and my replies to them. Try searching the forum for other questions about this issue and see some of the other responses that I have given. :)

Chrome 94.0.4606.71 Linux EasyEDA 6.4.25

andyfierman 2 years ago

Sorry, forgot to post the screenshot: ![image.png](//image.easyeda.com/pullimage/cVTRmlptFbpCWlBB9TeNvOXcoW88huJfi9eTt4s2.png)

Chrome 94.0.4606.71 Linux EasyEDA 6.4.25

Lorenzo Micheletti 2 years ago

I've totally missed the DRC errors, my bad! Thank you very much for your help.

Chrome 94.0.4606.81 Windows 10 EasyEDA 6.4.25

MikeDB 2 years ago

0 Ohm 1206 resistors can be your friend here. They actually force you to consider where the star point is as well.

Electron 4.2.10 Windows 10 EasyEDA 6.4.25

core3012 1 year ago

For me the solution was to use AGND, PGND, GND and proseed with my design. I also used prohibited regions where I want things to stay as they are. After everything was in place I applied PNGD on top layer and GND on bottom layer, placed all the vias I need and then simply went back to the schematic and replace all types of ground with GND. Rebuild all copper regions (shift+B). Thats it no DCR errors!

Chrome 108.0.0.0 Windows 10

andyfierman 1 year ago

@core3012, That's a clever solution but it will fail if after doing all that, you ever do **Update PCB...** or **Import Changes...**

Chrome 107.0.0.0 AndroidOS 10

你现在访问的是EasyEDA海外版，使用建立访问速度更快的国内版 https://lceda.cn(需要重新注册)
如果需要转移工程请在个人中心 - 工程 - 工程高级设置 - 下载工程，下载后在https://lceda.cn/editor 打开保存即可。
有问题联系QQ 3001956291 不再提醒

Cookie Notice

Our website uses essential cookies to help us ensure that it is working as expected, and uses optional analytics cookies to offer you a better browsing experience. To find out more, read our Cookie Notice

Unleash creativity, start design now.

Cookie Notice