Some questions: Have you given the track, via and copper area exactly the same net name? What happens when you make the copper area visible and rebuild it? What do your Gerbers show?

Just tested this on a simple PCB. Works OK for me in Firefox 57.0.4 as long as the track, via and copper area are given exactly the same net name. ![enter image description here][1] :) [1]: /editor/20180123/5a662a22cf68a.png

@andyfierman Hey, thanks for reply. Yes my net name is same on track, via and copper area. On the copper area I am able to see the via connected to the desired layer but ratlines are not disappearing giving me an impression of incomplete layout. Could it be a problem of me using google chrome (using Latest Version 63.0.3239.132 (Official Build) (64-bit)). As I see on your simple pcb it is working fine, for me too in such cases but my case is different in a few aspects. Let me try and explain my trouble again (sorry for the unintelligent question earlier) The image 1 shows the via in my pcb i am having trouble with, its net is +VSAM. on the either side of the said via there are two copper areas (Layer - Inner 2 in green colour), the +VSAM copper area is on the right which i wish to connect to the via (both highlighted). ![Layer top, inner2 visible][1] As you can see in the following image of only the Inner-2 layer, I tried to simply connect the copper area with the via trough a track which should effectively resolve both the ratlines attached to +VSAM but it does not. let me know how to do this because moving the via shall be difficult as the bottom layer is very busy in the vicinity of the +VSAM via. ![only Inner 2 layer visible][2] [1]: /editor/20180123/5a66ecc3826ef.PNG [2]: /editor/20180123/5a66f1f82e55a.PNG

@Pulkit Hi Please send your PCB as EasyEDA source to support@easyead.com I will have a look , thank you https://easyeda.com/Doc/Tutorial/Export.htm#Exporting-EasyEDA-Source

@andyfierman I have send the PCB as EASYEDA source file. Please keep it under strict Non Disclosure Agreement, its a projet i am trying to do for my company on your portal. Thank you for understanding. Pulkit

@Pulkit, Have you checked the Design Manager for any clues? ![enter image description here][1] [1]: /editor/20180123/5a671d74bcc87.png

Which email have you sent? support@easyeda.com haven't received yet.

And please notice, the editor doesn't support inner copper area or copper edge overlap now, you have to separate them. for example: ![enter image description here][1] left side is NG, right side is good. https://easyeda.com/Doc/Tutorial/PCB.htm#Copper-Area [1]: /editor/20180123/5a67247f4fe0e.png

I have regularly referred to design management as it conveniently highlights a net alone on pcb, on selecting the aforementioned +VSAM net, it shows the net on pcb as a set of +VSAM copper area, few connected terminals on components and the ratlines. My understanding is that as long as i see ratlines the connection are not complete. As the ratlines are showing i am inclined to believe that connection is not made. See in image the via V1 should be connected to the via V2 throught the copper area(green) under via V2. ![+VSAM Net highlighted][1] [1]: /editor/20180123/5a67294ceab22.PNG

`As the ratlines are showing i am inclined to believe that connection is not made.` Two questions: 1. Do the ratline still show if you save the file, close and then reopen it? 2. Do the Gerbers show that the tracks/pads/planes are connected?

Hi, I have sent a mail (sub - **Connecting tracks to copper area - thread**) from **maximuspulkit@gmail.com** with **PCB_02.json** attachment that i downloaded as given in tutorial. I have designed the copper area such that it satisfied the conditions you mentioned (non intersecting and no copper area inside a copper area on same layer). This should not be a issue. Replies to your ratline questions - 1. They still show after i save>close>reopen easyeda. 2. I just now tried doing a gerber, it seems like it is connected in gerber as seen in the image ![Gerber view of caopper area layer][1] [1]: /editor/20180123/5a6731028c4ee.PNG

@andyfierman Hey I think it wont work with copper area connected to a via (outside the copper area) through a track, on the same layer i had to connect the via (outside copper area) to the via (inside copper area) through a track within the same layer. The image should make it clear. The highlighted track is in the same layer as the copper area. ![Layer- only Inner-2 visible][1] [1]: /editor/20180124/5a68627c9bf10.PNG

@Pulkit, Well spotted! You are correct. It is not obvious but as at EasyEDA Version 5.1.3, the ratline will only be removed if: The length of track you draw on the same layer as a copper area to join a via or pad outside that copper area to that copper area is terminated at a pad or via within that copper area. If the length of track you draw on the same layer as a copper area to join a via or pad outside that copper area to that copper area is terminated within that copper layer but not at a pad or via within that copper area then the ratline will not be removed. In either case, however, the net will highlight correctly, will show as a connected net in the Design Manager and the Gerber files will be generated correctly. I have modified my demonstration project to illustrate this: ![enter image description here][1] ![enter image description here][2] This is a zoomed in view of the area: ![enter image description here][3] This is with the GND net highlighted: ![enter image description here][4] Note the ratline. This is the same area when the track ends at the GND via in the copper area: ![enter image description here][5] * Note that the ratline has gone. [1]: /editor/20180124/5a6881eb7b543.png [2]: /editor/20180124/5a68821a08277.png [3]: /editor/20180124/5a6877b578da3.png [4]: /editor/20180124/5a6877e551b1b.png [5]: /editor/20180124/5a68783654523.png

@andyfierman Thanks for the discussion here. I was able to complete my pcb this way. I will be back if i get stuck again. :)