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Connection cannot be made between via and through hole

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Thron1998 6 years ago

Hi all, I'm fairly new to the PCB scene and right now I'm trying to create my first small PCB. The image below is a screen capture from the current PCB layout. I wish to connect the TX hole from J1 (top pin) to the TX hole at J2 (right bottom). Which I wanted to accomplish this by using a via connection. But the traces do not connect as can be soon just below R1. I'm clearly missing something here, but I have no clue what it is. ![image.png](//image.easyeda.com/pullimage/R2hts47GRFNpwfJ2wbfcLmFM2deXXSSsfTasQ5KH.png) Down below is a picture of the schematic of the project:![image.png](//image.easyeda.com/pullimage/i7AMxVlnWQu6lWBbJg0XsrqP3pFLMxsZWdxcBn7f.png) Thank in advance!

Chrome 72.0.3626.96 Windows 10 EasyEDA 5.9.41

Comments

andyfierman 6 years ago

Please check the Design Manager in the right hand panel. It would be easier to diagnose if you could make the project public and post the link to it. Without access to your project however, I'd guess the pin mapping between the symbol and the PCB Footprint of J2 is wrong. Please note that you must include decoupling capacitors at the input and output of the AS1117 regulator according to the manufacturer's datasheet. [https://datasheet\.lcsc\.com/szlcsc/1812131418\_Youtai\-Semiconductor\-Co\-Ltd\-AMS1117\-3\-3\_C347222\.pdf](https://datasheet.lcsc.com/szlcsc/1812131418_Youtai-Semiconductor-Co-Ltd-AMS1117-3-3_C347222.pdf) Why? See: [https://easyeda\.com/andyfierman/Power\_supply\_decoupling\_and\_why\_it\_matters\_\-451e18a0d36b4f208394b2a2ff7642c9](https://easyeda.com/andyfierman/Power_supply_decoupling_and_why_it_matters_-451e18a0d36b4f208394b2a2ff7642c9)

Chrome 71.0.3578.98 Windows 10 EasyEDA 5.9.41

andyfierman 6 years ago

See also (4) and (6) in: [https://easyeda\.com/andyfierman/Welcome\_to\_EasyEDA\-31e1288f882e49e582699b8eb7fe9b1f](https://easyeda.com/andyfierman/Welcome_to_EasyEDA-31e1288f882e49e582699b8eb7fe9b1f)

Chrome 71.0.3578.98 Windows 10 EasyEDA 5.9.41

Thron1998 6 years ago

Hi andyfierman, This is the link to the, now public, project: [https://easyeda.com/Thron1998/ESP-programmer](https://easyeda.com/Thron1998/ESP-programmer) I imagine there are more faulty connections in the schematic, but I want to focus at one challenge at the time ;) And thanks for the tip regarding the decoupling capacitors. I will implement them soon. Greetings, Thijs

Chrome 72.0.3626.96 Windows 10 EasyEDA 5.9.41

andyfierman 6 years ago

The problem is that you have placed the via by hand and then not assigned the netname to it. You do not need to place vias by hand. Start the trace on your desired layer; left click once to end the track on that layer; press the letter or number key for the layer you want to swap the trace routing to (in your case if you started at J1 pin 4 on the Bottom layer you would press the T key to swap to the Top layer); A via will appear; Do not click anything: just continue routing on the new layer and end routing in the normal way adding more vias in the same way if required.

Chrome 71.0.3578.98 Windows 10 EasyEDA 5.9.41

Thron1998 6 years ago

Nice, that does the trick. Thank you!

Chrome 72.0.3626.96 Windows 10 EasyEDA 5.9.41

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