Your project is private so no-one but you can see it to investigate and help. For help on this please either make your project public or share it privately with support. Here's how to share: [https://docs.easyeda.com/en/Share/Share-to-Public/index.html](https://docs.easyeda.com/en/Share/Share-to-Public/index.html)

Hi Andy, I've added you as a member to the project. If you view 'PCB\_verb\_large2' in this project\, note the copper area on the left hand side of the top layer will not fill due to "copper area conflict"\. But to my eyes nothing is overlapping\. Thanks.

You have two copies of the PCB with the same name: **PCB\_verb\_large2**. Which one is the PCB that you are having a problem with? A quick check of the Design Manager shows that both of them have an unrouted section of the GND2 net between the highlighted pads:  Toggle the visibility of the Ratlines layer to see it more clearly. You also have at least one short section of unconnected track as in the short horizontal section of red track in the upper left of the above image. * Please check your design carefully using the Design Manager.

Hi Andy Yes\, that's the PCB I'm looking at\, I've renamed it "PCB\_verb\_coppererror" to avoid confusion\. The copper area (that I can't fill due to the conflict error) was to be assigned GND2 so the unrouted pads would be connected via the copper area. The error (big yellow 'X' upon opening the file) is still there. Not sure where I'm going wrong. Thanks.

I'll have another look.

OK, I'd missed the error messages and yellow cross warning because all the PCBs open in sequence rather than just the one you are asking about so the screen gets a bit cluttered as they open. The problem is that although the copper areas do not appear to overlap, there are edges that share exactly the same XY locations so EasyEDA sees that as an overlap. The only way to fix this is to move the edges very slightly apart to avoid coincident vertices. I had misunderstood the copper area "Clearance" attribute: it does not refer to a clearance between the edges of the copper areas. It is the clearance from pads surrounded by the copper area to the area itself when spokes are used.

Thanks a lot Andy. I have one last basic (and probably stupid) question... If I seperate the copper areas with a tiny gap, is it likely to cause problems during manufacturing? Or is there usually a solid board across the entire PCB that the copper areas are printed onto, something like that?

Good question! The clearance between edges of copper areas should be handled by the Design Rules but at present that is not what happens. I raised a bug report about this a while back but it seems to have stalled: [https://easyeda\.com/forum/topic/Copper\_areas\_with\_shared\_edges\_do\_not\_respect\_clearances\-Dd7CKSeAW](https://easyeda.com/forum/topic/Copper_areas_with_shared_edges_do_not_respect_clearances-Dd7CKSeAW) So to be safe you have to manually set the gap between the copper areas.