Your project is private so only you can see it. Please help us to help you by posting some screenshots or the url to a public project that demonstrates this issue. Thanks.

Project made public:  LiftMgt

Can't think of any further information/illustration to further describe my problem.  Do I have to remove all my manual routing and start over with the desired Design Rules?

@LiftMgt, Can you post the url to the public project here please?

  when I set the S1_P as rule 1, and check the DRC, it works

Project URL   [https://easyeda\.com/editor\#\,cmd\_for\_project=296c0eec097646ffbf5f222beceddb9a\,id=6c0ebba64ac8467daa403737262084ef\|0d89b012f7ab49bfa145035b3f363e85](https://easyeda.com/editor#,cmd_for_project=296c0eec097646ffbf5f222beceddb9a,id=6c0ebba64ac8467daa403737262084ef|0d89b012f7ab49bfa145035b3f363e85)<br> <br> I went to the Design Rule and noticed that the S1_P track was somehow set to Default.  I changed to Rule 1, selected "Apply", ran the DRC check and found no change in any of the DRC errors including that specific net.  I just can't get Design Rule 1 to act as the rule that applies to my design.  Basic question: After manually routing the entire board, discovering DRC errors, can one write a new Design Rule and cause it to apply to the design?

@LiftMgt, Sorry but this is why I asked you to make your project public: it is a waste of everyone's time trying to advise you on your choice of design rules because there are many errors in your PCB that need to be addressed before you worry about them. Here are a few (by no means all) examples: You have a track\, netnamed U2\_18 on the bottom layer but you have no via to swap the track onto the top layer to complete the connection to the left\-hand pad\, netnamed U2\_18 of R3\, which is on the top layer:  The footprint sfor DL1, DL2 and U6 are badly constructed and seems to have multilayer pads coaxially placed into holes:  which then cause DRC errors when routing tracks to them:  The footprints for DL1 and DL2 have pin numbers in the top copper layer which will short out any track that crosses them on that layer  You have tracks going through holes and a via in thr middle of nowhere:  Even after applying the updated Design Rules, you still have doznes of Via and Via Drill diameter and track to via DRC errors. You also have an incomplete GND connection:  <br> <br> C1 and C2 are in series. This unnecessary since the overall capacitance will be 100nF*10uF/(100nF+10uF) which is just under 100nF. I suspect you meant to connect them in parallel and not in series in order to provide 5V supply decoupling:  You have LEDs with a forward voltage of 1.9V that appear to be connected to inputs to the ATmega328P-MMHR. It is not clear what the function of these connections is but you should check that approximately 1.9V is a sufficiently high voltage to be seen by those inputs as a valid logic high and that the inputs are internally pulled down to ensure that when the switch associated with the LED is open circuit, the input is pulled to a valid logic low:  You should add extra, separate, decoupling on the VCC and AVCC pins of the ATmega328P-MMHR and probably on the AREF pin too.

Hi! I also want to point out that the pads inside the holes gets removed on DL1, DL2 and U2 Every pin is drilled and there is no copper to solder the pin into because it is now a standard ~1.6mm drilled hole. Am I right on my assumption? Regards, Markus Virtanen HW / Electronics Designer

@LiftMgt, As @markus_jidoka has pointed out, I should have clarified that the major consequence of my statement: "The footprints for DL1, DL2 and U6 are badly constructed and seems to have multilayer pads coaxially placed into holes:" is that those footprints will have holes of a bigger diameter than the pads and so will have no pads at all. It is completely unnecessary to add holes like this since multi-layer pads are specifically designed to created pads on all layers with a through plated hole joining them all up through the inner face of the hole. This project may help you understand the basics of PCBs: [https://easyeda\.com/andyfierman/Elements\_of\_a\_simple\_PCB\-e42c7b2a4e17449f821a97d04806aeeb](https://easyeda.com/andyfierman/Elements_of_a_simple_PCB-e42c7b2a4e17449f821a97d04806aeeb)<br> <br> Studying the Tutorial will help you understand how to use EasyEDA successfully. Reading and following the links in: [https://easyeda.com/forum/topic/How-to-ask-for-help-and-get-an-answer-71b17a40d15442349eaecbfae083e46a](https://easyeda.com/forum/topic/How-to-ask-for-help-and-get-an-answer-71b17a40d15442349eaecbfae083e46a)<br> <br> will give you a greater understanding of PCB design using EasyEDA in general.