@pamies, Welcome to EasyEDA. Please note that this is actually a question about PCB Layout and not about Schematic Capture so it would be helpful if you would edit your original post to change the **Category** of this topic to PCB Layout. Currently, EasyEDA does not support the assignment and passing of net attributes other than net names, from the Schematic Editor into the PCB Editor. Hence the PCB Editor has no visibility of any information about a net except the net name and it's connectivity within the schematic. The Design Rules therefore only apply to nets within the PCB Editor. In EasyEDA it is not currently possible to define individual design rules for different regions of the same net. However, since they are the same net, all the branches are at the same voltage and therefore they must have the same clearance, so that part of the question does not arise. The only way to deal with different trace widths at the moment is to manually change the trace width as you are routing. Or route them all as the widest track width then reduce the width of selected segments as required. If these tracks are important then they should be considered to be critical nets and therefore should be hand routed as the first - or at least very early on - in the PCB layout.

@pamies, If this feature is important to you, you might like to consider changing the Category of this topic to that of **Feature Request**. :)

Thanks @andyfierman.  Apologies for the incorrect category.  Have now edited.  I guess my thought had been that I could somehow define some form of wire junction in my schematic to allow branching of different nets. Since posting, I've been searching similar topics in this forum, and I've seen one idea (from you) that seemed similar to what I'm looking for... Could it be feasible for me to create my own schematic part and footprint that had two pins and was simply a pad of copper on the PCB, allowing two differently named nets to connect and use the pad as a junction?

Yes, but as you'll find from the various posts about it, that will generate DRC errors in the PCB because you are shorting what, in the schematic, are two separate nets together in copper in the PCB. The only way a 2 pin "net splitter" works without generating DRC errors in EasyEDA at the moment is if it is realised as a physical 0R resistor. This can be a 0R SMT resistor, a through hole wire link or a 2 pin header and jumper. Anything that just directly joins things together on copper on the PCB, whether it is done using tracks, pads, Footprints, Solid Regions or rectangles, will generate DRC errors. Adding 0R resistors is an expensive solution if the board is to be mass produced compared to the one time cost of manually editing the track widths. Specifying and finding 0R link components may be tricky at higher currents. This topic covers most of the points touched on above: [https://easyeda.com/forum/topic/Joining-two-different-copper-areas-7670ebb4cb4342849a7fa87e2b15346f](https://easyeda.com/forum/topic/Joining-two-different-copper-areas-7670ebb4cb4342849a7fa87e2b15346f)

@andyfierman You are an absolute start with the help you give everyone here. Thank you!

\* star\, not start

You're most welcome and thank you! :)

I raised a Feature Request about a net-splitter or net-tie back in February: [https://easyeda.com/forum/topic/Net-tie-a-copper-only-component-with-2-pads-to-split-nets-without-DRC-errors-and-multiple-netname-warnings-b6a099bf01bb4055b821ab398ee37b60](https://easyeda.com/forum/topic/Net-tie-a-copper-only-component-with-2-pads-to-split-nets-without-DRC-errors-and-multiple-netname-warnings-b6a099bf01bb4055b821ab398ee37b60) You could reply to it with "+1" to bump not up the ToDo list a bit. :)