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DRC Clearance Issue between Copper layer VCC to Copper layer GND
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Yariv Hashai 3 years ago
Hello, I have a top copper area of GND and a bottom copper area of VCC - hooking up WS2812b LEDs. I'm getting clearance issue DRC: ![Screen Shot 2021-01-30 at 10.29.28.png](//image.easyeda.com/pullimage/4fCtwd1GO6DXoqfL7cm4sVj8WgLGdREnAOUJFeSQ.png) The led it self has a VIA which connected to the VCC net ![Screen Shot 2021-01-30 at 10.32.34.png](//image.easyeda.com/pullimage/8pJThT9PJJoTFjWakDPcDpuFP3frurqjqAGE68Jl.png) And the error indicates that this is the issue: ![Screen Shot 2021-01-30 at 10.33.36.png](//image.easyeda.com/pullimage/l9fsFPcRW2q8TZdJyXiVrHLa5YXDSBeEdMWHOyb7.png) <br> <br> This is the copper area manager settings: ![Screen Shot 2021-01-30 at 10.34.17.png](//image.easyeda.com/pullimage/0MCf71557qLIu4BmQksOiU4VEeoSFDRzvRBrmTxZ.png)\ <br> Any suggestion on how to debug/fix this issue?
Comments
Yariv Hashai 3 years ago
Solved it be re applying the copper area - in case someone will have the same issue
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andyfierman 3 years ago
If the DRC error reappears when you refresh the PCB Design Manager again then the problem is because the LED Footprint has a via not a small pad in it. Please refer to: [https://easyeda.com/forum/topic/How-to-avoid-DRC-errors-when-connecting-to-PCB-Footprints-a-k-a-PCB-Libs-90bf944fe3644b21a7d27a9e9d8df8d6](https://easyeda.com/forum/topic/How-to-avoid-DRC-errors-when-connecting-to-PCB-Footprints-a-k-a-PCB-Libs-90bf944fe3644b21a7d27a9e9d8df8d6)
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