DRC Clearance Issues despite having defined a low enough value in the DRC
59 1
JFK422 2 months ago
Hi All So I stumbled upon this issue that I get a DRC clearance error despite having defined a lower clearance value in the DRC. This issue arises from the pads to vias and form the pads to pads. It happens with every package below 0.3mm. I tried replacing some packages with similar ones. Thou the same issue. ![DRC Readout](//image.easyeda.com/pullimage/IoTCY3lcRKSZbfYOycpFYSCpS7fdxNH8JtlMafje.png) ![DRC Issue example](//image.easyeda.com/pullimage/bAtqnFoOOItGL1SUNPfvZcP65KYySKDqFM8R9Pgo.png)
UserSupport 2 months ago
please ignore it by mind, EasyEDA doesn't support to ignore the footprint inside DRC error.
Login or Register to add a comment
你现在访问的是EasyEDA海外版,使用建立访问速度更快的国内版 https://lceda.cn(需要重新注册)
如果需要转移工程请在个人中心 - 工程 - 工程高级设置 - 下载工程,下载后在https://lceda.cn/editor 打开保存即可。
有问题联系QQ 3001956291 不再提醒
svg-battery svg-battery-wifi svg-books svg-more svg-paste svg-pencil svg-plant svg-ruler svg-share svg-user svg-logo-cn svg-double-arrow
We use cookies to offer you a better experience. Detailed information on the use of cookies on this website is provided in our Privacy Policy. By using this site, you consent to the use of our cookies.