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DRC Clearance errors with Network Arrays
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francesco.pesce 4 years ago
Hi all, this is my very first project, so maybe I am missing something. However I searched in the forum and did not find matches. I am planning to have some boards with SMT components mounted by JLCPCB SMT service. I am trying to use some very basic network arrays that are classified as "SMT type Basic" for JLCPCB SMT service, so I tought it was a good idea to use them: ![image.png](//image.easyeda.com/pullimage/jYCZIfHp9XPwtzYJ9d8WrElDVMseblpPQopVeL4B.png) But see what happens once you layout these components: ![image.png](//image.easyeda.com/pullimage/OnjMYvSpdyKJODLgx1D7L9PSkOEkbOnloW2w0kHb.png) It seems the pads of these components are not compliant with DRC rules. This sounds quite strange, as they are SMT-mountable by JLCPCB; they are 0603, so actually not really supersmall. Is there any way to solve this issue? Link to the project: [Clearance Test](https://easyeda.com/editor#id=|a6599bcad3e84d229c414beb7bf37af7|a6e80b95149d46449b41ec2c4f77de35) Many thanks! Francesco
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andyfierman 4 years ago
According to my sums, the gap between the end pad pairs is 0.135 mm = 5.315 mil | | | | --- | --- | | Pad widths (x in mm) | centres (x in mm) | | | | | 0.58 | 0.4 | | 0.75 | 1.2 | | Sum of half widths | Difference in centres | | 0.665 | 0.8 | | | Gap between = (Difference in centres) - (Sum of half widths) | | | Gap in mm | | | 0.135 | | | Gap in mil | | | 5.3149606299 | | | | Therefore when you check your PCB with a clearance of 6 mil it will throw DRC errors. The minimum clearance allowed by JLCPCB is 5 mil: [https://jlcpcb.com/capabilities/Capabilities](https://jlcpcb.com/capabilities/Capabilities) If you reduce the clearance to 5.3 mil in your Design Rules then the errors will disappear.
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francesco.pesce 4 years ago
Thank you very much Andy! That helped a lot, it works now. Appreciate your prompt help. I was thinking the DRC defaults were reflecting their capabilities, instead some values need to be adjusted. #solved
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