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DRC Clearance problem EasyEDA V6.1.52 Build Date :07/01/2019
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jackberg2012 4 years ago
EasyEDA V6.1.52 Build Date :07/01/2019 Placing an 78L05 (LCSC Part Number: C181132) and I've got an "Clearance Error" message. I tried different 78L05 from others, and still the same errors. This append when placing a trace from U5  to 78L05 pin 2.  (see picture 1) I have to delete the 78L05 to clear the clearance error. and redo the same, still the same error. To fix temporally I've had to re-edit the 78L05 pad # 2 (GND pad) to clear the error. (see picture 2) Maybe the default clearance dimensions need to be re-adjust (see picture 3) Is this an object (78L05) problem or an general clearance dimension from the user interface. Will appreciate any reply to fix this. Thank you **Picture 1** ![EasyEDA Bug-001.jpg](//image.easyeda.com/pullimage/wVdxlQybhfdRvKMdRdO7KHkIyzs5knsjzTEpxWcp.jpeg) **Picture 2** ![EasyEDA Bug-002.jpg](//image.easyeda.com/pullimage/a0RZY2JGwUYupPPwlhXcWRSTBmZrQSjY399gJP60.jpeg) **Picture 3** ![EasyEDA Bug-003.jpg](//image.easyeda.com/pullimage/RRACMqtptqUVKwHtF9E1oZNSeslgNItWBgVOuSq8.jpeg)
Comments
andyfierman 4 years ago
I'm not convinced you have solved the right problem. I have no problem routing to this part: ![image.png](//image.easyeda.com/pullimage/yZIklnjwUcFlDMSwnBkd1JBEDgzAVHdS5OWJbMj3.png) I think you need to check that: 1. there is not some other object in the same region as the number 2 pads for this footprint;  2. the clearance that you have set is not being affected by a rounding error between the displayed metric value and the underlying imperial values.
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andyfierman 4 years ago
As your project is private, only you can see it so this is a guess. * Did you route this PCB directly in the PCB Editor or did you create a schematic first and then do **Convert to PCB...** ?
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andyfierman 4 years ago
Yes. I reckon that's what you've done. For successful PCB design using EasyEDA, please read the Tutorial and follow the Design Flow.
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jackberg2012 4 years ago
@andyfierman I route this PCB directly in the PCB Editor. I delete this 78L05, and I did add an diode, then I've got 16 clearance errors. (see picture) What could be wrong, before adding an single diode and after to get all theses errors. I did few manual PCB layout with EasyEDA and it's work just fine. I did re-open my previous PCB layout with the new EasyEDA version, and I've got many clearance errors that was not there when I send theses for production. Thank 's for the reply ![EasyEDA Bug-004.jpg](//image.easyeda.com/pullimage/IbzRZUxaqIFroOJfw3eAYFvw3Kdk5DYGISWdiZ99.jpeg)
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jackberg2012 4 years ago
to: @andyfierman Hi, I did re-design the relay board, with few parts. I add an 78L05 , traced manually the pin 1 and 3, checked the DRC = ok after routing the trace for pin 2 (Gnd) to the block terminal then checked the DRC, and I've got an error pointing to the 78L05 pin 2 pad. (see picture) Thank's andy for the reply. ![EasyEDA Bug-005.jpg](//image.easyeda.com/pullimage/lupvVKV3KECvPRPoYK2I96cLe4dP9acysnxHSu6d.jpeg)
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andyfierman 4 years ago
If you follow the recommended design flow you won't get this kind of problem. If you want to design a pcb directly in the pcb editor then you must use the Connect Pad to Pad tool. [https://easyeda\.com/forum/topic/How\_does\_the\_Connect\_Pad\_to\_Pad\_tool\_work\_\-JgQO0Ay7H](https://easyeda.com/forum/topic/How_does_the_Connect_Pad_to_Pad_tool_work_-JgQO0Ay7H) If you follow the Design Flow and then start editing directly in the PCB,  you will create all sorts of problems. The proper route is to make changes to packages, netnames, connectivity and BoM information in the schematic and then pass that into the pcb using the Update PCB... or Import Changes... tools.
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jackberg2012 4 years ago
@andyfierman Hi, Andy thank's for your help. usually I always draw manually on the PCB Editor, my PCB's are a low quantity of parts (10 resistor,some IC's,and few other parts) for me it's faster to produce this way, also that EasyEDA software is much refine than my old DipTrace (under 300 pins capacity). I'll look at the link you send to me asap, to learn as much on the Pad to Pad connect toll. My Best regards.
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jackberg2012 4 years ago
Hi, Andy I found some notes that I took a year ago concerning this problem, and what it's come is by deleting all the Nets reference number, this actually solve this problem for all "Via's" and other pad and traces on the PCB Editor. I did draw the PCB directly without any previous schematic and it's working ok. To verify this, I did upload the Gerber files to JLCPCB, and checked the final result in the Gerber view. The PCB files are just fine. (see pictures) Thank's again. Regards. ![EasyEDA Relay Module-1.jpg](//image.easyeda.com/pullimage/PfsbCJEEMnNgSpbU2Ys70Y9AU8YlCEeY3WTYLEFI.jpeg) ![EasyEDA Relay Module- Gerber.jpg](//image.easyeda.com/pullimage/z2to1elL4oF2T6b7HJUU5m458IspgRDf6ogrAO8p.jpeg)
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UserSupport 4 years ago
You need to read the tutorials [https://docs.easyeda.com/en/PCB/Design-Rule-Check/index.html](https://docs.easyeda.com/en/PCB/Design-Rule-Check/index.html)
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UserSupport 4 years ago
It should clear for the error detail ![图片.png](//image.easyeda.com/pullimage/ChmGw58uZNMNM04MfBnNx1xS0BCoU9AYJruDjoPh.png)
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jackberg2012 4 years ago
Hi User Support I'll read it. Thank's again.
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andyfierman 4 years ago
Basically you have to assign the same netname to everything connected to a net: track segments, pads, vias. Then you avoid any connectivity based DRC clearance errors.
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jackberg2012 4 years ago
Thank's again Andy
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