I've just encountered a funny bug, on default DRC settings (via 0.61mm) every via on my PCB gets a DRC Error, somehow 0.61mm on the PCB is different then 0.61mm from DRC rule. Changing DRC rule to 0.609mm removes annoying errors (but doesn't solve the problem)

Chrome
84.0.4147.125
OS X
10_14_6
EasyEDA
6.4.5