Why are the connection lines even show up when the tracks are already connected?
And anywhere this happens has a DRC error of clearance. Any idea why?
It would help if you could make - and post the link to - a public project demonstrating this issue.
Otherwise just guessing...
* For each net, check that the netnames of the pads and the tracks connecting them are all the same (eyeball the PCB and use the Design manager to identify nets).
* Is this PCB created from an EasyEDA Schematic in the same project folder?
* Have you assigned netnames in the schematic?
@andyfierman Here is the link to this project. I have checked the net names, they are all the same. The PCB is created from an EasyEDA schematic in the same project folder, but it was updated a few times. Some net names are assigned, but some are not.
[https://easyeda.com/ss4c0001/h-bridge-inverter_copy](https://easyeda.com/ss4c0001/h-bridge-inverter_copy)
@andyfierman I have figured the problem out. The two pads that are being connected has the same net name, but the track does not. It seems like when I updated the PCB, the net name of the tracks does not get updated. This needs to be fixed.
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