To preface my question, this is my first PCB design, and am new to both EasyEDA and the terminology used in PCB design. With that said, please let me know if I am doing something stupid, or using incorrect terminology in the below description. I have a 2-pin JST connector that supplies 9V power to my PCB; 1 pin is 9V signal and the other is GND signal. The JST connector footprint has 2 multi-layer pads accordingly. I need to connect the common ground trace to this 2nd pin on the JST, labelled as 'U3_2' in the PCB (see first 2 pictures).   However, when I go to drag the GND trace over this U3_2 pad, I get a yellow X, and an associated design rule error regarding clearance (see picture 3).  The only explanation for this (to me) is that EasyEDA doesn't like the non-matching net names, even though they are connected in the schematic. I have the same DRC error for pin U3_1. My questions then are as follows: 1) How can I rectify the DRC error? 2) If I can't, can I create the trace and void the DRC errors? Will I still be able to get the PCB manufactured? Any help would be greatly appreciated. Thanks.