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DRC Failing even thoe everything is visibly connected
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Wyalt 3 years ago
Hello. During my work on a project for a game controller. The DRC gave me back an error on the GND Net ( same as the copper area used and all the connections/vias) even though it's visibly connected as you can see in the picture. In this case, the ground plane is on the bottom layer and therefore blue. \- The screen is only part of the whole project but i tought there was everything needed\. ![image.png](//image.easyeda.com/pullimage/u3jtUC4SoX6rPErDT0oPZAoZYrVxIye3yDJMBFs2.png) Is this supposed to happen & I'm doing something wrong or it shouldn't? What should i do?
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andyfierman 3 years ago
Youf screenshot does not give enough information because at present it is unclear what is unconnected. You also have not described the board stack up. It looks like it is more than 2 layers. If so how are the layers assigned? First thing to do is to make everything except the Ratline layer invisible. Look for the ratlines showing incomplete connections then turn on other layers to help identify exactly where and what is not connected yet.
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Wyalt 3 years ago
Hello! I tried importing the file on the online editor. Somehow I had only this problem on the original file, not on the imported one, I also tried cloning it ( by copy/pasting it ) and there were no problems with the GND Net. So i guess it's fixed Thanks anyway for the help and have a great day!!
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Wyalt 3 years ago
Nevermind! Spoke too soon, I tried exporting it as a Gerber and the problem came back. as mentioned before, checking the DRC alone without trying to export it doesn't give me errors Btw the PCB is a 2 layer board. I tried checking missing connections through ratline and I had no missing connections. I would like to share the file but somehow it doesn't let me. I will try again later, in case it doesn't let me after, is it ok if I give you a google drive link?
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Wyalt 3 years ago
It came through my mind right now. Is it possible that the missing IC's on the EasyEda Project is causing the errors? All of the missing connections are between pins/pads that should be connected to 1 stm32 and/or the PWM Manager
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andyfierman 3 years ago
@Wyalt, "Is it possible that the missing IC's on the EasyEda Project is causing the errors?" At the risk of stating the obvious, how can anyone tell you that without sight of your project? :) This might help: [https://easyeda.com/forum/topic/How-to-make-a-Project-public-and-share-the-links-to-it-9f006513b84b412580910905b0281d20](https://easyeda.com/forum/topic/How-to-make-a-Project-public-and-share-the-links-to-it-9f006513b84b412580910905b0281d20)
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Wyalt 3 years ago
It didn't let me share it cause it wanted "30 minutes" even though I waited more than 30 mins. here is the file [https://oshwlab.com/Wyalt/gc02](https://oshwlab.com/Wyalt/gc02)
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andyfierman 3 years ago
Your background colour makes it very hard to see the Ratlines so I set it to white. Mouse-X and Mouse-Y shows roughly where they are. ![image.png](//image.easyeda.com/pullimage/YVWGf31vLcMd3WzKXtLYvF7wjcag6RqEudz13ezh.png)
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andyfierman 3 years ago
You can also find the Ratlines more directly by using the new **Net Ratlines** feature in the **Design Manager**: ![image.png](//image.easyeda.com/pullimage/Sv3aZRF81vEKOhRvQdcgI2IdedgU402HkfP5Rnsp.png)
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Wyalt 3 years ago
I ended up checking it and it's also a pad that should be connected and pass trough an IC. So i guess the mis-connections are due to the missing IC's
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andyfierman 3 years ago
@Wyalt, "So i guess the mis-connections are due to the missing IC's" We can help you find the ratlines but most peoples' powers of deduction fail when presented with a design that includes undisclosed missing devices. :)
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