![Sans titre.png](//image.easyeda.com/pullimage/KdClQnHzqDPaBM4IWmhnO1ZtzCCnmVpPA0tEMIJa.png)Hi,
I am trying to design a 2-layer PCB and I have many DRC errors as well as "net" errors on the 2 integrated circuits ... I tried to change the rules of DRC but nothing helps ...
There is probably something that I do wrong!
I do not know how I should do to make the project public ...
Thank you in advance for your help.
Firefox
68.0
Windows
10
EasyEDA
6.2.41