I'm getting a DRC error on my layout for all VIAs - dozens of them.
When I click on one, it's complaining that the holes are _0.61mm (24mil)_ but the rule requires _0.61mm (24.016mil)_. I didn't do anything to change any DRC rules.
It seems a small rounding error on the mils
Obviously, this isn't good because it could be hiding a real error.
Chrome
93.0.4577.82
OS X
10_13_6
EasyEDA
6.4.25