Clearance error is between pad on bottom layer and capacitor pad on top layer
With capacitor - DRC error (ignore other one - it's same thing elsewhere)
![image.png](//image.easyeda.com/pullimage/qr3h0GW9VlaahiO8vk62yeISTfD2ns230z9kLi2C.png)
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And with capacitor deleted - DRC error gone
![image.png](//image.easyeda.com/pullimage/Q3qq9VhbY4O5cP1ziqbBDlR9bMyI4fvzV8i9N7AO.png)
This worked fine until today
Electron
4.2.10
Windows
10
EasyEDA
6.4.16