Clearance error is between pad on bottom layer and capacitor pad on top layer
With capacitor - DRC error (ignore other one - it's same thing elsewhere)

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And with capacitor deleted - DRC error gone

This worked fine until today
            
                        
            
                                    
              
                Electron
                  4.2.10
                Windows
                  10
                                EasyEDA
                  6.4.16