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Schematic PCB Simulation Skill Extension Feature Requests Bug Reports

Design Rules - Net to Net Rules

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cjohnson 4 years ago

**Description of Feature:** Ability to create net to net rules in the design rules window. These rules will create DRC errors if the distance between the specified nets is violated. **Why:** Some designs will have high voltage and low voltage on the same board. The distance between the high voltage (if they are the same polarity) does not need to be the same distance as the distance from that high voltage net to lets say ground, +5V, +3.3V, etc. Basically what I'm doing right now is setting the rule of my high voltage nets to the higher distance rule, then ignoring DRC errors of high voltage -> high voltage.

Chrome 74.0.3729.157 Windows 10 EasyEDA 6.1.48

Comments

andyfierman 4 years ago

That's what this is for: [https://docs.easyeda.com/en/PCB/Design-Rule-Check/index.html](https://docs.easyeda.com/en/PCB/Design-Rule-Check/index.html)

Chrome 73.0.3683.86 Ubuntu EasyEDA 6.1.48

cjohnson 4 years ago

@andyfierman I understand how to use that, and I'm using that. What I'm saying is it would be nice to say the clearance between lets say +5V and GND can be the default settings (6 mil clearance), but the distance between LINE (265 volts or whatever) and +5V needs to be atleast 44 mil (or something). Right now the design rule tool is limited in that it can only specify the distance between +5V and ANY net, not a specific net.

Electron 2.0.5 Windows 10 EasyEDA 6.1.48

MikeDB 4 years ago

Agreed - it is the voltage difference between tracks that matters, not the absolute voltage on that track. That said a lot of IPC and other PCB safety standards do specify absolute voltage rather than the difference.

Electron 2.0.5 Windows 10 EasyEDA 6.1.48

cjohnson 4 years ago

@MikeDB Yea, in most cases high voltage high voltage creepage or clearance distance is very small compared to high voltage low voltage. In this case we are trying to meet SELV with a new design. We have the spec, but basically I'm just having to ignore all the DRC errors that are my LINE net to other high voltage nets because those distances don't matter in my case.

Chrome 74.0.3729.169 Windows 10 EasyEDA 6.1.48

andyfierman 4 years ago

@cjohnson, OK, I understand your question better now. You also have to consider what the voltage differences may be during power up and down in case one HV supply comes up before another. Another case may be what the difference could be if there were a fault in one rail adjacent to another that caused it to be much lower than the clearance between them was designed for.

Chrome 73.0.3683.86 Ubuntu EasyEDA 6.1.48

cjohnson 4 years ago

@andyfierman Not for what we are designing for, they are just relay contacts. We know what is hooked up to them, per customers design, this has more use cases then just mine either. It would be extremely helpful to set trace to board edge clearances separate from the net clearances.

Chrome 74.0.3729.169 Windows 10 EasyEDA 6.1.48

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