Could you explain why? Clearances are primarily governed by two things: 1. the voltage differences between copper features; 2. the minimum clearances stated by the PCB manufacturer to meet their process requirements. Once you have satisfied those requirements, the next consideration is that of maintaining adequate separation between traces to meet crosstalk requirements or in the case of controlled impedance traces, the target characteristic impedance. In none of these cases does there appear to be a need to be able to specify a different clearance for tracks as opposed to vias.

Hi It will be implement at EasyEDA pro edition, and it has free plan too, maybe will launch at 2021.06

@UserSupport, Interesting but I still don't understand why there might be a need to be able to specify a different Design Rule clearance for track-track and track-via. I understand the need for different minimum spacings in the PCB fabrication process but not in the design rules for PCB layout.

@andyfierman The complicated design needs more complicated design rules, we will support a lot of design rules in pro edition