please check the DRC setting, and change the DRC size smaller
[https://docs.easyeda.com/en/PCB/Design-Rule-Check/index.html](https://docs.easyeda.com/en/PCB/Design-Rule-Check/index.html)
if these vias are placed by auto- router, that is a known issue.
thanks
Our website uses essential cookies to help us ensure that it is working as expected, and uses optional analytics cookies to offer you a better browsing experience. To find out more, read our Cookie Notice