What have you changed in the Schematic between PCB updates? Netnames?

Before correction   After fixing and clicking the button, update the board  

Not enough information because there are no netnames visible in either the schematic or the PCB. Check that the netnames of the wires you have joined are consistent in the schematic and in the PCB after the update. If you converted to PCB before you changed the nets then the tracks in the original PCB will have the netnames from the original PCB. If you then change the connectivity of the schematic and then do update PCB you may have created inconsistent net names by joining wires with different net names together in the schematic. If the netnames in the PCB are already applied from the original schematic there may be a conflict after the update. Can you make your project public or add me or support to your team to share it privately?

Here is a clone of the project, if you click the refresh button, this error will appear [https://easyeda\.com/AlekssII/copy\-plk3\_copy\_copy\_copy](https://easyeda.com/AlekssII/copy-plk3_copy_copy_copy)

@AlekssII, In: [https://easyeda\.com/AlekssII/copy\-plk3\_copy\_copy\_copy](https://easyeda.com/AlekssII/copy-plk3_copy_copy_copy) the ratlines that appear for example around R45 in your screenshot are because in the original PCB you had a lot of things connected to a net named R50\_2\. You also had a lot of things on a net named R57\_1\. After you joined the two nets in the schematic\, the net name of the resultant\, merged net changed from R50\_2 to R57\_1\. All the pads of the footprints associated with the pins in the schematic that are now named R57_1 in the PCB. The tracks are however still named R50_2 so the tracks no longer represent the updated electrical connectivity. You will have to either reroute or find each incorrectly named track segment and manually rename it You also however have a large number of serious DRC clearance errors that need to be addressed. I have not looked through all of them but several are caused by net name mismatches. For example:  Whether these are the result of tracks being incorrectly or incompletely routed is unclear. You also have many incomplete nets because you have started routing with an incomplete or you have altered the component placement. Whatever the reasons for this are you need to complete the placement and then the routing before worrying about ratlines that may or may not be the results of incorrect or incomplete connectivity. Also, please note that it is not good practice to put documentary information, such as dimensions, on the silk screen layers. Such information should be placed on the Document layer

Your issue set me thinking... Please see this Feature Request: [https://easyeda.com/forum/topic/Option-to-update-track-names-in-PCB-on-Update-PCB-Import-Changes-0d55a48c6f0041db8b6a97ed875bec7f](https://easyeda.com/forum/topic/Option-to-update-track-names-in-PCB-on-Update-PCB-Import-Changes-0d55a48c6f0041db8b6a97ed875bec7f)

@andyfierman thanks for the answer ) I realized that the names are different, but decided not to re-enter the names, but redrawn. The sizes are just for me, after I delete them.

Hi EasyEDA doesn't support update the track netname automatically, please change it maually.

@UserSupport [It's No Good](https://www.google.com/search?q=it%27s+no+good+(u.s.+maxi+single)&stick=H4sIAAAAAAAAAOPgE-LVT9c3NExJqbA0Tik0VIJwk7PL09OryvK01LOTrfRzS4szk_WLUpPzi1Iy89Ljk3NKi0tSi6zSMouKSxQSc5JKcxexymeWqBcr5OUrpOfnpyholOoV6ynkJlZkKhQDteSkagIAnhMv2msAAAA&sa=X&ved=2ahUKEwilnI6hmfflAhUMlIsKHUV6DUcQmxMoATAFegQIDBAV)