There's not enough info in your screenshot to see what might be the cause. What happens if you click on the entries in the lower panel? What do the Net Pins show and what happens if you click on the Net Pins entries in the lower panel? What does VBUS show in the upper panel? Can make it (or an edited demo) public or add me to your Team?

@andyfierman Thanks andy! I have added you to my team :)

Got it. The close spacing of the VBUS vias have left tiny isolated islands in the Inner 1 (ground) plane:  There is no attribute in inner layer planes to select **Keep Islands = No**. I have raised a Feature Request for this: [https://easyeda.com/forum/topic/Please-add-Keep-Islands-Yes-No-attribute-for-inner-plane-layers-0fdc9076d80045d5b9210f650274a83b](https://easyeda.com/forum/topic/Please-add-Keep-Islands-Yes-No-attribute-for-inner-plane-layers-0fdc9076d80045d5b9210f650274a83b)

@andyfierman Wow thanks! That makes sense. I also manage to come around it by changing the layer 2-3 to signal. And then manually add the GND planes to those signal planes.

 If other have the same problem. On the left is when you do PLANE with a 4 layer board. On the right is when you add a GND plane to the layer that is selected as a SIGNAL layer in a 4 layer stackup. The tiny island of GND is unconnected when using the PLANE function.

You could also remove the islands in this particular example by increasing the clearance around the VBUS net. However, at present, it seems that replacing the plane layers with signal layers and then placing copper areas on them to replace the dedicated plane layers stops the crippling slow-down in PCB editor performance so it is the right thing to do now anyway.. :)