With reference to your image above, what happens if you remove the two pairs of mouse bite holes that straddle inside and outside of the board areas?

I removed middle ones from all of the panel pieces and get the same endless loop feature: 

Not the middle ones. The two pairs, one pair at the end of each of the slots.


Same behavior. I'm going to try and remove all of them and see what happens. If it works, I might just have to copy them out into another file and paste in after i rebuild the copper area.

Ugh, even with them all removed, i get the endless loop: 

Is this the cause of your problem? [https://docs.easyeda.com/en/PCB/Panelize/index.html#Panelize-by-Manually](https://docs.easyeda.com/en/PCB/Panelize/index.html#Panelize-by-Manually)

i don't know. that's not exactly a descriptive issue. also, in the above image, as far as EasyEDA is concerned, it's not even a panel.

Hmmmm. If they are 4 layer boards, what happens if you delete the plane layers?

I can't find daxliniere's original post about this but it might be related to #3 in: [https://easyeda.com/forum/topic/All-the-problems-with-EasyEDA-and-why-I-ll-switch-to-Flux-AI-etc-ed439d0f90104d2980cd09aa14f83cd9](https://easyeda.com/forum/topic/All-the-problems-with-EasyEDA-and-why-I-ll-switch-to-Flux-AI-etc-ed439d0f90104d2980cd09aa14f83cd9)<br> <br>

Honestly, this whole panelization experience between EasyEDA and JLCPCB is super frustrating. The tools in EasyEDA for paneling are really designed around cheap ass v-score boards.  The mouse bites stuff is absolutely useless. So if you want to spin a high quality panel (with routing and mousebites), you have to do it manually - which is fine, except for all the bugs that this introduces. And near as I can tell, there is no way to order panels from JLCPCB the way that I order panels from every other board house we work with. With everyone else, we provide two sets of gerbers, the first is the individual file:  And then we provide a gerber set for the panel:  And then the board house puts them together. I really wish there were a way to do this with JLCPCB, because the current workflow is super frustrating, given the bugs/limits of EasyEDA. <br> <br>

@andyfierman none of them are "plane" layers. they're all signal.