Hello, I recently updated my desktop version to 6.5.1 and things seemed fine initially, however I have created a new pcb design using a previous board outline from another project and I am seeing a lot of really strange things going on when trying to connect traces manually. If I put in a JLC part number and pull a part from the catalog, lets say a resistor, it starts out with no pad net names. In the past I could make a trace and connect to pads, if both pads being connected did not have net names the system would generate a new net name for the trace and both pads automatically. If one of the pads already had a net name then the new trace and pad that was being connected with use the existing net name. In a case where both pads already had net name, connecting a new trace between different net names would ask if I would like to replace the net name on the part I was connecting to. What I am seeing now has me very confused and I can only assume this is a bug. If I have to pads with no net names and I try to draw a trace between them the system stops me from connecting the trace to the second pad. I have to click off the trace and then reselet the trace to finish making the connection. If the trace was coming from a part I created the net name for I can not manually rename the pad on the part I am trying to connect with by typing the name in. It lets me type the name and I've tried hitting enter and tab after entering the name but the pad name fails to save. What I have found is that using control + C and control + V I can rename pads and they will save the name once they are clicked off of. Thinking I was losing my mind, I go to another project and check how this is behaving and its working exactly like I would have expected and how it's worked for as long as I can remember. What I've found was that if I create a new blank pcb project and then copy in my pcb outline in 2 sections saving after each section is added and closing the project then reopening  the project after added each section before I reconnect the 2 parts the program works exactly how I would expect it to. Since I've figured out how to work around the issue for now it's no long a problem but since this is clearly unintended behavior that has only shown up since the last update I figured this must be a bug of some sorts. I have not deleted the project this bug is currently present in just in case it would be helpful in understanding what is happening. Because the pcb design is part of a commercial closed source product I can not publically share a link to this but I would be happy to share the project with the EasyEDA team so other users don't run into this issue in the future. I spent several hours trying to figure out what was going on and have been using EasyEDA since around 2017 so I've very experienced with it, for a new user or someone less experienced this bug would likely be enough of an issue that they would never consider using EasyEDA for anything. I would also like to add that the "new" size of net names is making me VERY unhappy. There is no reason that initial net names need to start out with something like_**S$7392962564878632,**_when using 0603 or 0402 size parts the net names are extending into the part next to each other.  I understand there are reason net names could get that large but for a "small" project there is no reason for names to be that large.