Need "stitching" caps between power on 3rd layer and GND plane on 3rd layer without including other layers.
Can I have limited length vias or do I need to remove copper on layers 1,2 & 4 so vias only touch layer 3 PWR and layer 3 GND plane? My signals and PWR are not directly above each other as in photo I do not want vias piercing other GND planes
Electron
19.1.9
Windows
10
EasyEDA
6.5.34