You need to give more information.

What does the PCB Design Manager show in the left hand panel when you run the DRC and when you click on any highlighted indications?

How many layers and, if more than two, how are the inner layers assigned?

Your project is private so only you can see it to investigate.

Can you make your project public?

Thanks for your reply Andy,

• The DRC panel displays the following:
  
• The PCB contains 4 layers and the distribution is: top and botton for routing, inner1 is VDD33 and inner2 GND.
• I turned my proyect to public.

Thanks,
Cristian Correa

I think you may be having the same problem as described in this topic:

https://easyeda.com/forum/topic/Inner-layer-plane-connect-to-Top-bottom-layer-tracks-df4ebd41e1114705b795f3da06f627d1



It quite a long thread but please take the time to read through it and follow the links.

Hello!

You have not yet published your project. I would like to take a look...

Regards,

Markus Virtanen
HW / Electronics Designer

@criscorrea, As @markus_ee says, your project is not yet public.

It will help you to read:

https://easyeda.com/forum/topic/How-to-make-a-Project-public-and-share-the-links-to-it-9f006513b84b412580910905b0281d20



:)

@andyfierman @markus_ee

https://oshwlab.com/teamindor/smart_grow_sensor

Hi!

I got it fixed when I changed the layer type from "Plane" to "Signal".

I don't usually use "plane" layer construction method because it is a bit more complicated and sometimes buggy.

-Markus

There is also a small "oopsies" in the PCB outline at bottom left corner:

There is also an error in the schematic:

I can go through the errors and publish a corrected version...

Thank you very much, @markus_jidoka !! :)

Hi!

I just published the corrected version:

https://oshwlab.com/markus_jidoka/smart_grow_sensor

@markus_jidoka you're very kind! Thanks!

You're welcome. Let me know if you need further assistance in the future.

-Markus