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Exists incomplete connection
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criscorrea 1 year ago
<span class="colour" style="color: rgb(55, 65, 81);">Hi,</span> <span class="colour" style="color: rgb(55, 65, 81);">I'm working on a PCB design with LCSC parts. In the schematic, I connected the 17th pin of two ICs to GND, as shown in the first picture.</span><br> <br> ![schematic.png](//image.easyeda.com/pullimage/BdBEccFnmU2vKhtMy6I3jIuErWP4X3ZpwKRjTIZH.png) However, in the PCB design, there seems to be an incomplete connection between those pins (pin 17 of the two ICs). ![pcb.png](//image.easyeda.com/pullimage/WhLofJtYAeEumLvoBOyRioZchF29tKEvEt3r3RkQ.png) This incomplete connection is completely wrong because, as you can see in the schematic, R10 pins are supposed to be connected to VDD33, C10, and DVI. Can someone help me with this? <span class="colour" style="color: rgb(55, 65, 81);">Thanks,</span><br> <br> <span class="colour" style="color: rgb(55, 65, 81);">Cristian Correa</span>
Comments
andyfierman 1 year ago
You need to give more information. What does the PCB Design Manager show in the left hand panel when you run the DRC and when you click on any highlighted indications? How many layers and, if more than two, how are the inner layers assigned? Your project is private so only you can see it to investigate. Can you make your project public?
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criscorrea 1 year ago
Thanks for your reply Andy, * The DRC panel displays the following: ![drc-error.png](//image.easyeda.com/pullimage/iSTxSuaTfzNqOGK8kyZkg7FfC411aaFBc5aIkqtD.png) * The PCB contains 4 layers and the distribution is: top and botton for routing, inner1 is VDD33 and inner2 GND.  * I turned my proyect to public. Thanks, Cristian Correa
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andyfierman 1 year ago
I think you may be having the same problem as described in this topic: [https://easyeda.com/forum/topic/Inner-layer-plane-connect-to-Top-bottom-layer-tracks-df4ebd41e1114705b795f3da06f627d1](https://easyeda.com/forum/topic/Inner-layer-plane-connect-to-Top-bottom-layer-tracks-df4ebd41e1114705b795f3da06f627d1)<br> <br> It quite a long thread but please take the time to read through it and follow the links.
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Markus_ee 1 year ago
Hello! You have not yet published your project. I would like to take a look... Regards, Markus Virtanen HW / Electronics Designer
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andyfierman 1 year ago
@criscorrea, As @markus_ee says, your project is not yet public. It will help you to read: [https://easyeda.com/forum/topic/How-to-make-a-Project-public-and-share-the-links-to-it-9f006513b84b412580910905b0281d20](https://easyeda.com/forum/topic/How-to-make-a-Project-public-and-share-the-links-to-it-9f006513b84b412580910905b0281d20)<br> <br> :)
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criscorrea 1 year ago
@andyfierman @markus_ee [https://oshwlab\.com/teamindor/smart\_grow\_sensor](https://oshwlab.com/teamindor/smart_grow_sensor)<br> <br> ![Captura desde 2023-08-02 06-51-43.png](//image.easyeda.com/pullimage/DCBtxRntS1ZYFVTo6zQPmhUIUzirSr6aByZQvezy.png)
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Markus_ee 1 year ago
Hi! I got it fixed when I changed the layer type from "Plane" to "Signal". I don't usually use "plane" layer construction method because it is a bit more complicated and sometimes buggy. -Markus
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Markus_ee 1 year ago
There is also a small "oopsies" in the PCB outline at bottom left corner: ![image.png](//image.easyeda.com/pullimage/GhnBjGsnbuDoOfkMnAbkquyMDN6lGzjnlpufDqxz.png)
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Markus_ee 1 year ago
There is also an error in the schematic: ![image.png](//image.easyeda.com/pullimage/vjjtnXZHfh1mOzsxpY3ZesLaUJMv3mM4sA3VRWum.png) I can go through the errors and publish a corrected version...
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criscorrea 1 year ago
Thank you very much, @markus_jidoka !! :)
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Markus_ee 1 year ago
Hi! I just published the corrected version: [https://oshwlab\.com/markus\_jidoka/smart\_grow\_sensor](https://oshwlab.com/markus_jidoka/smart_grow_sensor)
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criscorrea 1 year ago
@markus_jidoka you're very kind! Thanks!
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Markus_ee 1 year ago
You're welcome. Let me know if you need further assistance in the future. -Markus
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