Hi, After EASYEDA changed to a new version today it finds many DRC errors on by PCB layout. but most of them seems false errors. For example it shows pad-to-pad error between vias which are more than 10 mils appart. (I measured the distance on Gerber files with another software):  My setting for pad-to-pad design rule was 7 mils. I then tried changing the setting to 5 mils and there are still the same number of errors after refresh of DRC errors. On the other side, It shows TRUE DRC errors than weren't detected by the previous version of EASYEDA yesterday:  My project is public: davri/dav\_training\_1 Thanks for your help