For first PCB layout, you have done a great job, but I don't know what you mena best way to router, EasyEDA has auto router.

Hi Carlbenjaminsmith, Welcome to EasyEDA. Your layout is fine as a first attempt at PCB layout. None of the traces look like thay will have to carry any especially high currents or voltages so the thin traces you have laid down are OK. The only thing I would suggest is that it is generally good practice to only join (or split traces at right anglesrather than the 45 degree forking you have used on the GND trace between U3 and U4: ![enter image description here][1] Please also note this post: https://easyeda.com/forum/topic/Net_naming_conventions-uOHBvN5nh You do have a couple of thngs to fix in the routing of the GND and 5V traces: 1) You need to insert some vias: ![enter image description here][2] to swap the GND traces from the bottom to the top layer to connect with the pads on the top layer. 2) Same issue with the +5V traces. The easiest fix for this is to route the +5V traces on the top layer. Even better is if you do this and then add a big rectangular copper area covering just outside the whole of the top layer assigned to the +5V net and another one on the bottom layer assigned to the GND net. Select the dashed outline of each copper area in turn and then click on `Rebuild Copper Area` in the right hand panel. Just use the default settings for the copper layer in the right hand panel. Make sure you route any traces into pads in the centre of the pad edge at right angles to the pad because this will then be overlapped by the heat shunt `Spokes` of the copper area. (You'll see what I mean if you try it.) In fact if you use the copper area, you don't need to route to the +5V pads because they are already assigned to +5V so will automagically connect to the +5V copper area when you rebuild it. For the GND pads you still need to have a short trace from each GND pad to a via to swap the connection to it onto the bottom layer. The copper area will then automagically connect to each of these GND vias on the bottom layer when you rebuild it. That will fill all the available area of the top layer with the +5V net and on the bottom with the GND net. It will also connect the GND pins on both sides of the shield. That significantly reduces the impedance of the GND and +5V routing. Don't forget as you do all this to keep checking the Design Manager in the right hand panel to check that you have all the footprints placed, nets connected and have no DRC Errors: ![enter image description here][3] Finally, before submitting the order to EasyEDA for your PCB, please check this post: https://easyeda.com/forum/topic/Essential_checks_before_placing_a_PCB_order-UuohztL3l :) [1]: /editor/20161207/5847cc84461a6.png [2]: /editor/20161207/5847ccfc4c498.png [3]: /editor/20161207/5847d1c5a5abb.png

In your layout, when inserting the vias, all you need to do is to drop a via onto the trace and then select the segment of trace between the via and the pad and swap it from bottom to top layer in the right hand panel: ![enter image description here][1] [1]: /editor/20161207/5847d4a132612.png

So I figured a way to get all my traces on the surface. However, the ratlines still want to connect to GND and IOREF (which is also +5v) even those those pads are connected to GND and +5V through other traces. Any idea? ![enter image description here][1] This is the only way I was able to get rid of the ratlines and all the net errors. ![enter image description here][2] [1]: /editor/20161208/58485db18ffa5.png [2]: /editor/20161208/58485ddf5e49f.png

Can you make your latest version of the project public?

Leak Checker PCB Rev 2 is now public. Thanks Andy

There seems to be a problem with the UNO_R3 PCB footprint. Please see Bug Report: https://easyeda.com/forum/topic/Problem_with_UNO_R3_PCB_footprint_-VpjdvNGYg We'll sort this out as soon as we can. One question: is this a footrpint you made yourself or is it an EasyEDA footprint?

Ah! The UNO_R3 footprint has been imported from a Sparkfun Library. I have updated the bug report.

Here's a workaround: 1. Please replace your UNO_R3 footprint from the `System components` with the new one with the same name from `User Contributions`. 2. In your schematic, please to add all the required wires to complete the +5V and GND connections between the shield and U1 - U5. Your schematic must show all the necessary connectons. The problem was that the original footprint had netlables already assigned to the pins and some were wrong anyway. It is not normal practice to assign netlables to the pins of library parts. That is normally only done when the part is placed into a PCB as part of the automatic `Convert Project to PCB` process. Sorry about the confuson this has caused.

The UNO_R3 PCB footprint in the EasyEDA library is now fixed (and my local copy has been deleted).

Awesome. Thanks!

@andyfierman Thanks for your help! This project turned out awesome. (and saved my company an immense amount of $$$)