When opening your project: [https://easyeda\.com/editor\#id=\|e7718541907543c5a1b21312ba615ac0\|4aa2bd8772d14d31b430cb49d94da761](https://easyeda.com/editor#id=%7Ce7718541907543c5a1b21312ba615ac0%7C4aa2bd8772d14d31b430cb49d94da761) it seems to get stuck rebuilding the copper areas of the PCB:  If I cancel the Building Copper Area box and go to the PCB and then do Shift+B to Rebuild All Copper Areas then it's fine. I have posted this as a Bug Report: [https://easyeda.com/forum/topic/Opening-project-gets-stuck-rebuilding-the-copper-areas-of-the-PCB-e2803ece67b94e6c8b93734069b5772d](https://easyeda.com/forum/topic/Opening-project-gets-stuck-rebuilding-the-copper-areas-of-the-PCB-e2803ece67b94e6c8b93734069b5772d)

Sorry but you still have lots of clearance errors:  You might like to have a look at a test project I made whilst trying out different ideas for the LED footprint: [https://easyeda.com/andyfierman/cree-ledxpe2-demo](https://easyeda.com/andyfierman/cree-ledxpe2-demo) Check through the PCB a layer at a time to see what's going on and how it's constructed. The symbol and footprint are those described in my recent reply to: [https://easyeda.com/forum/topic/Routing-traces-ends-up-moving-ratlines-ef1de9be2eec4931b4cc4e0693e8fbd0](https://easyeda.com/forum/topic/Routing-traces-ends-up-moving-ratlines-ef1de9be2eec4931b4cc4e0693e8fbd0):  Symbol: [https://easyeda.com/component/9051501de1be4f5095eeb5e8b9b024a7](https://easyeda.com/component/9051501de1be4f5095eeb5e8b9b024a7) Footprint: [https://easyeda.com/component/1cac84fae82c4ca285532856916286aa](https://easyeda.com/component/1cac84fae82c4ca285532856916286aa)

Thank you so much for the reference project.  That was a big help. At this point, I believe I have created a functioning board with proper traces and connections.  There are no DRC errors and all of my nets seem connected. I would like to learn how to create the copper areas surrounding each LED pad I had on the previous design. Is there a simple way to explain that process or could you direct me to one of your write ups that explains that process.  The documentation is cumbersome compared to your concise and clear instructions, so I would prefer materials sourced from you, if possible. Amazing support.  Thank you, Andy.

link to new design . . . [https://easyeda\.com/editor\#id=\|e7718541907543c5a1b21312ba615ac0\|886743b364c24ebeae2503f95687566a](https://easyeda.com/editor#id=|e7718541907543c5a1b21312ba615ac0|886743b364c24ebeae2503f95687566a)

updated design with ground plane and copper areas . . . [https://easyeda\.com/editor\#id=\|e7718541907543c5a1b21312ba615ac0\|78b436db241d4873a15722cd5feb561e](https://easyeda.com/editor#id=|e7718541907543c5a1b21312ba615ac0|78b436db241d4873a15722cd5feb561e)

@darryl.lawler, Glad the demo project helped. "...how to create the copper areas surrounding each LED pad I had on the previous design." I'm not clear which one you mean. Could you post a screenshot or a link to it? I think I need to write a feature request to ask for a negative paste mask expansion (so that a paste mask can be smaller than the pad area). I also need to add a section to (2.3) in: [https://easyeda\.com/andyfierman/Welcome\_to\_EasyEDA\-31e1288f882e49e582699b8eb7fe9b1f](https://easyeda.com/andyfierman/Welcome_to_EasyEDA-31e1288f882e49e582699b8eb7fe9b1f) to better explain how to create footprints so that they avoid DRC errors. The trick is to forget about trying to map a small number of device symbol pins onto what may be a larger number of footprint pads and instead to just "number" the footprint pads with the functions of the symbol pins like in this symbol and associated packages: [https://easyeda.com/component/18e109ce9a4f4f6cabf206a788dc10de](https://easyeda.com/component/18e109ce9a4f4f6cabf206a788dc10de) [https://easyeda.com/component/395d4bdb97334f5697ad6103aaf4fb50](https://easyeda.com/component/395d4bdb97334f5697ad6103aaf4fb50) [https://easyeda.com/component/afaaaf8f819e42f384ee4403af5ce36f](https://easyeda.com/component/afaaaf8f819e42f384ee4403af5ce36f)

@andyfierman, Thank you for your reply. The copper areas I described are what you can see in my most recently linked revision of the PCB. I have deleted the first version, so you might have to go to my project page and open the PCB from there. [https://easyeda.com/darryl.lawler/test2](https://easyeda.com/darryl.lawler/test2) The large copper areas I have surrounding each anode and cathode are what I was describing. I also followed the documentation you included with the footprint and manually created the traces you described.  I was hoping this would address the thermal pads aperture challenge you've been describing. Would you say my PCB is ready for manufacture or are the issues with the footprint pads you describe in your post above going to prevent the board from working?  I'm definitely grateful for you creating the footprint and once I used it,  the traces seem to function, but I'm not going to trust my inexperience. At this point, the traces seem redundant given the copper areas, but I left them since I noticed you left the GND traces in your example PCB.

@darryl.lawler, A few points. At the moment you have set the copper area connections into pads as "Spoke". This is good practice because if you select "Direct" you get a solid connection into the copper area which makes a good joint for high current capacity but makes it very hard to solder. You can see the spokes in the upper pad of the LED in this screenshot (for clarity, I turned off visbility of the silkscreen). You can also see however that the H3_2 track that you have added does two things. It fills in one quadrant of the spoked connection to the header pin in the lower right and it does the same in the lower right of the LED pad.  This defeats the object of having the heat shunting spokes. You don't need these tracks for connectivity although, if you prefer, you can add tracks like these but it is good practice to adjust their widths and align them so that they cross and overlap the spokes with the same or smaller width. That then preserves the structure of the spokes. Like this:  A more subtle point about adding tracks when you have spoked connections to a copper area is that you can accidentally create tiny holes in the PCB that may trap etching fluids and cause problems with long term board reliability. This is unlikely to be a problem with modern board production techniques but is best avoided. You can see an example of one of these holes in the upper left of thetop LED pad in the image below. The highlighted track on the upper right illustrates how the hole arises. Just for comparision purposes, I have deleted both tracks to the lower pad and set the lower copper area connection style to "Direct" to show what a solid connection to the pad with no additional tracks, would look like, should you prefer to do it that way.  The last point is that although your ground strip up the centre connects OK, if copy your project and then do **Update the PCB...** or **Import Changes...** I get DRC errors for every set of three centre pads on all the LEDs. If, howwever, I then add a GND connection to the third pin of every LEDin the schematic:  save it, do **Update the PCB...** or **Import Changes...** and then run a DRC on the PCB, there are no errors. It's a lot to get the hang of and I still make mistakes and overlook stuff even now. That's why we recommend people make some test projects and just play with the tool before starting a bigger, more complex and often time critical project but you've borne with us and got there OK now. Well done! It's also prompted me to find ways to tackle some more complex symbols and footprints and highlighted some things EasyEDA needs to do better. :)

Amazing support.  Thank you for providing the level of detail you have in your responses.  Beyond the initial hurdle of needing a functioning footprint, you helped foster my understanding of multiple best practices in PCB design.  Thank you. I agree with retaining the spoke connection for the copper areas throughout the whole board to avoid soldering challenges.  I have implemented that change.  I have also connected all of the LEDs to GND as suggested.  Hopefully that eliminates the rebuild errors you were experiencing. I have also started cleaning up the copper areas so they aren't leaving little remnants around the round solder pads.  I think I should be close to RTM, if you see anything else I might be missing, please let me know. Thank you for all of your help.  You represent EasyEDA very well.

Unless it has got broken in V6, you should not need to tidy up the copper fragments (islands) because there's already a setting in the copper areas panel: Keep Island = No :)

I understand.  Thank you. I believe the board should be ready for manufacture at this point.  I will review your linked instructions from the previous post for finalizing a design for submission to JLCPCB. If you see anything I might be missing, please don't hesitate to mention it. Your help has been essential.

One more thing to do: If you turn off everything except the top layer you'll see that the centre line pads are not joined by a manually-added-after-placement1.3mm wide track I referred to in the footprint notes:  * If you add that from the centre of the left hand centre pad to the centre of the right hand centre pad;  * rebuild all the copper areas (SHIFT+B); * refresh the DRC check in the Design Manager panel * select the track and click **Expose Copper; ** then you should get:  which should end up looking like:  with no DRC errors.

Darn.  I had those short thermal traces there at one point and for some reason deleted the Top Layer trace after exposing the copper.  Genuinely have no idea why I thought I needed to do that, but I've fixed it now. I have reoriented the board vertically, to panelize it and make best use of the stencil area limitations at JLCPCB.  I am hoping I followed the correct procedure for panelizing 5 boards.  LMK, if you can. Thank you

New revision.  Interested in any feedback. I increased the size of the GND plane to which the thermal pads were attached.  Hopefully this will achieve the required thermal dissipation on the board.  I realize I will need to address ambient thermal management and use proper sinking on whatever I attach the board to. Are 1.3mm traces wide enough for 1 - 1.5A?  I have no interest in driving these LEDs at that current.  I just want enough copper there for extenuating circumstances. Would like to panelize this, as seen in the design (5 boards total).  Do I need to put a border or to include vertical/horizontal spacing between each board?  I'm unsure of what JLCPCB requires in this respect. Thank you for any and all comments, tips, suggestions . . . [LINK](https://easyeda.com/editor#id=|e7718541907543c5a1b21312ba615ac0|78b436db241d4873a15722cd5feb561e|ae9d79140b8d486bbf0ee6a0b271b17e)

Updated. [LINK](https://easyeda.com/editor#id=|e7718541907543c5a1b21312ba615ac0|78b436db241d4873a15722cd5feb561e|ae9d79140b8d486bbf0ee6a0b271b17e)

Version using copper areas for anode/cathode connections.  This helps to maximize the connection to the anode/cathode solder pads. [LINK](https://easyeda.com/editor#id=|e7718541907543c5a1b21312ba615ac0|78b436db241d4873a15722cd5feb561e|ae9d79140b8d486bbf0ee6a0b271b17e|cc1d0004e68f4d929405c17b3808bc2b)

I'll try to have a look tomorrow. Two things to consider: if you cover the back of the PCB with ground plane you could add thermal vias to the thermal pad region to increase the thermal coupling to this additional back-face heatsinking. The drawback is that for the vias to be effective they should be solder filled but if they are then effective your soldering has to guarantee that this thermal pad is properly soldered as the vias defeat the use of the thermal relief spokes. This is a contradiction that I have not found to be well explained in most apps note for devices with these thermal pads.

@andyfierman - thank you for your continued assistance. I have added vias to the board.  Not directly under the thermal pad, but flanking each LED.  I have also elected to pour over the relief spokes around the thermal pad in an effort to aid in thermal transfer.  I realize this will require some experimentation when it comes to the soldering process, but I can deal with that. Here is the latest revision with all updates.  [LINK](https://easyeda.com/editor#id=|e7718541907543c5a1b21312ba615ac0|78b436db241d4873a15722cd5feb561e|ae9d79140b8d486bbf0ee6a0b271b17e|cc1d0004e68f4d929405c17b3808bc2b) This revision includes the use of copper pours for the Anode/Cathode connections.