I'm just about done wiring up a medium-to-large schematic and I am having some nets on logic chips misbehave in the Design Manager tab, under Nets. I have made all of the connections to GND and VCC like any other component, but I have multiple nets that do not cooperate. Any ideas or solutions? I have tried deleting wires and re-running them to no avail.

Edit/Solution: Always check user submitted libraries if you get this error!
Electron
3.0.11
Windows
10
EasyEDA
6.4.5