I'm just about done wiring up a medium-to-large schematic and I am having some nets on logic chips misbehave in the Design Manager tab, under Nets. I have made all of the connections to GND and VCC like any other component, but I have multiple nets that do not cooperate. Any ideas or solutions? I have tried deleting wires and re-running them to no avail.
Edit/Solution: Always check user submitted libraries if you get this error!
I made a copy of the schematic, and due to the confidentiality of the project I began to delete components that did not affect the error. After deleting the 555 circuit which used the inverter at its output, the error went away but could not immediately trace it to the inverter. I would have never realized the error if I hadn't gone through and deleted 95% of my project, I wish the design manager had just a little more help!
The culprit was a 7406 inverter library submitted by JacoAlb.
https://easyeda.com/zvolk4/vcc-gnd-issue
@zvolk4,
Good that you have found the issue but please note:
"Edit/Solution: Always check user submitted libraries if you get this error!"
You must always check user contributed Schematic Symbols and PCB Footprints before using them.
It is a good idea to check them anyway no matter which library they come from.
If you find a problem with any Schematic Symbol or PCB Footprint please submit an Error Report.
Brand new interactions and interfaces. 
Easy to use and quick to get started. 
The message at the bottom of the left hand panel tells you exactly what is wrong.
Click on the nets and they will highlight and the Editor will zoom to the highlighted net so you can inspect the netlabel to see or investigate and correct the problem.
From your screenshot, it looks like this is what you are doing but it is not clear.
Can you make a copy of your schematic or a part of it that demonstrates this issue and post the url for it here?