Please make your project public and post the project url.

I have it in my computer.  I don't know how to share it.  Also, the MOSFET is a custom component.

[https://easyeda.com/forum/topic/How-to-copy-projects-created-and-saved-in-Desktop-Client-Projects-Offline-mode-to-the-cloud-780e8ed79d474be9a36e1568f220089b](https://easyeda.com/forum/topic/How-to-copy-projects-created-and-saved-in-Desktop-Client-Projects-Offline-mode-to-the-cloud-780e8ed79d474be9a36e1568f220089b)<br> <br> then: [https://easyeda.com/forum/topic/How-to-make-a-Project-public-and-share-the-links-to-it-9f006513b84b412580910905b0281d20](https://easyeda.com/forum/topic/How-to-make-a-Project-public-and-share-the-links-to-it-9f006513b84b412580910905b0281d20)

You can copy and paste your LTspice netlist here.  Reply to this post: insert a Code Block:  then paste your copied LTspice netlist into it. <br> <br> <br> <br>

\*\* Sheet\_1 \*\* R1 R1\_1 R1\_2 13K RP1 RP1\_1 R1\_1 47K C1 C1_1 GND 33N C2 GND C2_2 352N C3 C2\_2 C3\_2 100N R2 RP1\_1 C2\_2 13K R3 GND R3_2 1K R4 GND C3_2 1M XSC1 XSC1\_1 GND GND GND XSC1\_5 XSC1\_6 XSC1\_A XSC1\_B OSCILLOSCOPE XU3 GND C2\_2 XU3\_3 R1\_2 C1\_1 C2\_2 R1\_1 R1\_2 555\_BJT\_EE XU1 C3\_2 XU1\_2 R3\_2 IXFH120N15P V1 XU1_2 GND 12 RP2 R3\_2 XSC1\_1 GND 2\.5K V2 R1_2 GND 12 \.Save V\(XSC1\_A\) V\(XSC1\_B\) .SUBCKT  OSCILLOSCOPE 1  2  3 4 5 6 7 8 B1 7 GND V=V(1,2) B2 8 GND V=V(3,4) .ENDS <br> <br> <br> <br> .tran 10m \.inc EDA/555\_BJT\_EE\.SUB \* PSpice Model Editor \- Version 9\.2\.1 *$ .SUBCKT IXFH120N15P G D S \*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\* *Note:                                                              * \* Althought models can be a useful tool in evaluating device        \* \* performance\, they cannot model exact device performance           \* \* under all conditions\, nor are they intended to replace            \* \* bread boarding for final verification\. Therefore IXYS does        \* \* not assume any liability arsing from their use\.  IXYS reserves    \* \* the right to change models without prior notice\. The Pspice model \* \* does not constitute product data sheet\. Designer should refer to  \* \* the data sheet to guranteed the limit and specification\.          \* \*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\* \*\* model generated on October 2\, 2012 \* Node 1 \-\> Drain \* Node 2 \-\> Gate \* Node 3 \-\> Source R_ds D 9 0.0070 R_gs G 70 0.1 L_s Sg S 1n R_S S11 Sg 0.0032 M111 9 70 S11 S11 MM111 L=1u W=30u .MODEL MM111 NMOS LEVEL=1 +IS=1e-32 +VTO=4.65 +LAMBDA=820.88605e-05 +KP=1.00 E_rv 70 DG 70 S 1 D_DS DG D DRV .Model DRV D + CJO=5.1435E-9 + M=1.0293 + VJ=8.7160 + N=10 Cin G S 5n * L_bd S2 S 1n D_1 S2 D BD .MODEL BD D + IS=97.007E-18 + N=.72156 + RS=2.8404E-3 + IKF=1.0000E3 + CJO=5.3416E-9 + M=.7075 + VJ=1.0213 + ISR=29.162E-9 + BV=149.90 + IBV=25.938E-3 + TT=60.893E-9 .ENDS *$

\*\* Sheet\_1 \*\* R1 R1\_1 R1\_2 13K RP1 RP1\_1 R1\_1 47K C1 C1_1 GND 33N C2 GND C2_2 352N C3 C2\_2 C3\_2 100N R2 RP1\_1 C2\_2 13K R3 GND R3_2 1K R4 GND C3_2 1M XSC1 XSC1\_1 GND GND GND XSC1\_5 XSC1\_6 XSC1\_A XSC1\_B OSCILLOSCOPE XU3 GND C2\_2 XU3\_3 R1\_2 C1\_1 C2\_2 R1\_1 R1\_2 555\_BJT\_EE XU1 C3\_2 XU1\_2 R3\_2 IXFH120N15P V1 XU1_2 GND 12 RP2 R3\_2 XSC1\_1 GND 2\.5K V2 R1_2 GND 12 \.Save V\(XSC1\_A\) V\(XSC1\_B\)\.SUBCKT  OSCILLOSCOPE 1  2  3 4 5 6 7 8 B1 7 GND V=V(1,2) B2 8 GND V=V(3,4) .ENDS .tran 10m \.inc EDA/555\_BJT\_EE\.SUB \* PSpice Model Editor \- Version 9\.2\.1 *$ .SUBCKT IXFH120N15P G D S \*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\* *Note:                                                              * \* Althought models can be a useful tool in evaluating device        \* \* performance\, they cannot model exact device performance           \* \* under all conditions\, nor are they intended to replace            \* \* bread boarding for final verification\. Therefore IXYS does        \* \* not assume any liability arsing from their use\.  IXYS reserves    \* \* the right to change models without prior notice\. The Pspice model \* \* does not constitute product data sheet\. Designer should refer to  \* \* the data sheet to guranteed the limit and specification\.          \* \*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\* \*\* model generated on October 2\, 2012 \* Node 1 \-\> Drain \* Node 2 \-\> Gate \* Node 3 \-\> Source R_ds D 9 0.0070 R_gs G 70 0.1 L_s Sg S 1n R_S S11 Sg 0.0032 M111 9 70 S11 S11 MM111 L=1u W=30u .MODEL MM111 NMOS LEVEL=1 +IS=1e-32 +VTO=4.65 +LAMBDA=820.88605e-05 +KP=1.00 E_rv 70 DG 70 S 1 D_DS DG D DRV .Model DRV D * CJO=5.1435E-9 * M=1.0293 * VJ=8.7160 * N=10 Cin G S 5n * L_bd S2 S 1n D_1 S2 D BD .MODEL BD D * IS=97.007E-18 * N=.72156 * RS=2.8404E-3 * IKF=1.0000E3 * CJO=5.3416E-9 * M=.7075 * VJ=1.0213 * ISR=29.162E-9 * BV=149.90 * IBV=25.938E-3 * TT=60.893E-9 .ENDS *$

Nevermind.  I can't share my project.  It kept asking me to use EasyEDA for 30 min.  Not sure why there is such requirement but I am going for other simulation software.

The two versions of your netlist both have problems due to the forum posting and parsing process so it is not clear if this line in your second netlist posting:  is what your netlist is really showing or if it is the result of a forum parsing error. If your netlist really is showing that, then that explains the error message but it is not obvious how this netlist error arises. So we still need to see your public project...

@phucly, The30 minutes rule is to try to reduce the huge number of spammers that EasyEDA attracts. You could simply download the EasyEDA Source (.json) file and email it to me @easyeda.com If you do want to use other simulation software, I would recommend LTspice. Or the now freeware Microcap12 and Superspice are quite good too.