Here's the contents of the bottom solder mask file `G04 Layer: BottomSolderMaskLayer*` `G04 EasyEDA v6.1.41, Mon, 13 May 2019 23:03:07 GMT*` `G04 c99c01774ca941119f5b769db914f477,3b8503088de04cf78c269de7bbaf0aa3,10*` `G04 Gerber Generator version 0.2*` `G04 Scale: 100 percent, Rotated: No, Reflected: No *` `G04 Dimensions in inches *` `G04 leading zeros omitted , absolute positions ,2 integer and 4 decimal *` `%FSLAX24Y24*%` `%MOIN*%` `G90*` `G70D02*``%LPD*%` `M00*` `M02*`

I think I have figured it out, but still am unsure how to respond to the JLC rep. If there is no exposed copper on the bottom (vias only, no through hole pads) it generates an empty solder mask gerber. This file isn't formatted or generated correctly though, because gerbview sees it as an invalid file.

I recently created a simple test board with a layer with no copper and saw much the same thing and I think this may be the same issue that koosjr was having problems with a couple of weeks ago on his front panels. Have a look with gerbv? ( The FOSS Gerber viewer)

@andyfierman Ah, that makes sense. So what I did to fix this was exposing the copper on the vias that I have on my board. It doesn't matter to me that the vias are covered in soldermask. This created a valid bottom solder mask file and now it looks correct in JLC's gerber viewer and in my local GerbView software. This is **definitely** a **bug** in the solder mask gerber file generator.

I agree. I have just created a project with three simple PCBs: [https://easyeda.com/andyfierman/front-panel-with-silkscreen](https://easyeda.com/andyfierman/front-panel-with-silkscreen) 1. One has no copper at all. 2. One has a track on the bottom and a solid region on the top with no exposed pads or copper on either side. 3. The third has a track with 2 multi layer pads and a couple of solid regions, one with the region set to Expose Copper. There are some other features but they are irrelevant to this discussion. In (1) and (2) the top and bottom Soldermask files (.GTS and .GBS) are identical, suggesting that they are void. Only in (3) do they contain any data. This suggests that a non-void Soldermask file is only generated when there is an aperture in the soldermask due to some area of exposed copper. In other words if there is an area of copper with none of it exposed then a void soldermask file is generated which seem to be treated as NO SOLDERMASK REQUIRED.

@andyfierman That observation correlates with what I have seen as well. If this is the case, then koosjr's EasyEDA project was valid, but the gerber generation in EasyEDA is what is causing the problem with JLCPCB orders lately.

please send your PCB as EasyEDA file to [support@easyeda.com](mailto:support@easyeda.com) I need to check your file, and please let me know whehter if you want the bottom layer to create the solder mask layer when you placing an image? Are you want to make the logo copper exposing?

@cjohnson For koosjr's issue, that is JLCPCB quality issue, not EasyEDA gerber generater bug. if your PCB doesn't have any object which will create the solder mask (like Pad, solder mask layer object), ther Gerber generater will not generate the solder mask graphics.

@UserSupport I disagree.The gerber generation is not correct. If the back side of the board is just vias, without copper exposed, the bottom soldermask file is invalid. It can't be opened by any gerber viewer as myself and Andy have tested. This is how the board is **supposed** to look:  The graphics you saw in my original post were in the silkscreen, not the solder mask. This is the exact same board, but with the copper on the vias exposed. It fixes the bottom soldermask generation problem. This is 100% a bug, because it caused the gerber generation from koosjr's board to not generate a valid solder mask file, since there was no apertures in the design itself.

@UserSupport Also, would like to add that this is a recent bug, not something that's always been there. I recently ordered these exact boards and generated gerber files were correct. Looking at the differences between the same design I ordered recently and the current gerber file generation, it appears that EasyEDA stopped putting a small soldermask aperture in the center of via holes.  This is how the bottom solder mask looked on the same design in that previous order.

@cjohnson, Good spot!

@andyfierman One thing this doesn't answer though, is that even if the gerber generation created the pinholes for the vias, it would still not work for a design with no vias/pads at all. It would generate a blank solder mask file and JLCPCB will treat that as "no solder mask."

Agreed. I think the default should be that a soldermask layer is generated irrespective of whether; 1. there is copper on the layer **and**; 2. any part of the solder mask contains an aperture **or**;  3. unless the user states otherwise **or**; 4. the user states that the board is to be single sided. For cases (3) and (4) then the relevant soldermask file(s) MUST be deleted from the generated gerber file archive by the user before submitting the gerber file archive for quote and manufacture.

@andyfierman Yep, the implementation portion of this is a little tricky.

@cjohnson For the via, EasyEDA will not generate the solder mask for the via hole. then you will not see the solder mask data when the PCB only placed the vias. I agree this image, that control by Gerber viewer, the product should be like this too.  For solder mask layer: [https://en.wikipedia.org/wiki/Solder_mask](https://en.wikipedia.org/wiki/Solder_mask) it is a negative layer, which area you want to expose copper, you need to create a solder mask object for it.  you can refer at: [https://www.eurocircuits.com/pcb-design-guidelines/](https://www.eurocircuits.com/pcb-design-guidelines/) 

@UserSupport I understand fully that the file is a negative, that isn't the issue here. The issue is that when you generate a gerber file that doesn't contain any apertures in the soldermask file, JLCPCB's gerber viewer doesn't show it having a soldermask at all.

When I generate below PCB gerber file at v6.1.41, v.5.9.42, v5.8.20, v5.7.26, v5.6.15, the top or bottom solder mask gerber file contents are the same,  it should not a recenlty bug, EasyEDA generate it all the time, but we will figure it out whether if correct or incorrect. thanks  

Right Oaks, I will sum it up as I experience it. 1\. I design my PCB on EasyEDA\. 2\. With all finished\, I press the button to push it through to JLCPCB\. 3\. EasyEDA asks me if I did the DRC checks etc and I confirm\, please make that Gerber\. Now, keep in mind that like many people, I make face plates from PCB materials. Why? It is strong, drilled perfectly, the "paint" does not come off, the printed text is extremely durable. This is the thing you use if you want a robust board that does duty in the field. Yes, some of them have zero copper on it, but we also do copper when there are LED's and things punched through it. 4\. Right\, now the Gerber is generated and pushed trhough to JLCPCB\. Lets assume it is one of those with no copper that caused this trouble\. 5\. JLCPCB loads the Gerber\, and shows "Success\!" in the popup\, but all of a sudden the dimensions are erased and one has to put them back in by hand\. \(At this point I think it is only reasonable to expect that an ordering system should be able to read every single Geber generated by the design system\.\) Yet, no image shows, but I can select the colour, double or single sided, PCB thickness and so fourth. I as user have no indication or reason to believe that there might be something wrong in the background that I am not aware of, that will casue my PCB NOT to be the colour I selected. Surely one can at least not be too surprised that if you say 1-sided, then only 1 side could be colour. There are however not options for zero-sided or one that says no colour. From and end-user point of view, at that interface, the most logical expectation is that you get a PCB at the colour that you chose. However, since the page does NOT display the image of the PCB as normal, yet the Gerber was not rejected, and I also was not warned about the possible conflict I think everything is fine. If you ask your Granny to look at the order page and say what she thinks she wil get, what will be her answer? Surely not that Green actually means Clean. 6\. I think one could comfortrably say that the actual number of PCB's where clients really wants no colour on any side\, will be by far in the minimum\. Probably less than 1% of the total number of boards manufactured\. There simply is little application for it\. 7\. So\, it is in my mind as simple as this: 99% of boards will need colour on at least one side\. If your system absolutely needs the solder mask layers to be generated for a side to be colour\, you need to generate both\, always\. Copper\, no copper does not matter\. If the PCB has a silk layer on both sides, then surely there would be very little reason not to colour both sides simply for the ease of reading the text. 8\. If the user then goes to the order page and select single side and a colour\, then a single side needs to be colour \- the side of the silk layer with text on\. If he selects double sided\, then both sides has to be colour regardless of copper or silk layers\. 9\. If you really neally need to cater for boards where copper is needed with NO solder mask \(and we do need that for high current boards where you top up tracks with solder\)\, then it must be a DELETE OPTION for one or both sides\. That is an advanced option that I reckon will be no issue for experienced designers to grasp\. If I am in a hurry and things go wrong, I will rather have a solder mask and scrape it off from tracks, then needing colour and not have it.

@koosjr They have actually recently implemented the "DELETE OPTION" for copper. It's the Expose Copper button when a trace or copper region is selection. I especially agree on the color, if I choose a color, no matter what the board should be colored. There are very few applications, except single sided boards, where soldermask is not desired. If the engineer at JLCPCB is unsure if soldermask should or should not be applied, contacting the customer is definitely the first option he should choose. First and foremost, soldermask should always be applied unless a soldermask file is NOT supplied in the gerber upload. If the soldermask file is present, it better have soldermask on it when the board is manufactured.

Okay I'm trying to submit a front panel as described above and the picture on the JLCPCB upload site shows a light brown image rather than green so there is obviously no solder mask.  I don't have anywhere hidden I can put any components so how do I guarantee the solder mask to be applied over the whole board ?

@MikeDB specify in the comments box that both sides require soldermask. I have to do it everytime with our stencil orders to get the orientation correct.

Yes but I wanted something more definite as I don't have the time to fix an error.  What I have found is making the 3U mounting holes a library symbol with exposed copper which actually helps grounding seems to be forcing the website to show a soldermask.  Vias and the library holes didn't do this so it thinks they are components.

@MikeDB well you're out of luck there. They read the comments now and are much better about ensuring you get what you want. You can also specify in the checkout to not pay until it goes through approval. My last 10 or more orders have been completed successfully and they have manufactured according to the comments .

@cjohnson Oddly enough, I always get them to check first but I can't get the pre-pay box to untick at the moment so I've asked support to fix it.

Got the same issue on a rather large order so I was about to place another one now and found a workaround that works for me (as of today at least). I simply placed an SMD resistor off the board AT THE COPPER SIDE you want the mask to be added. Haven't got the boards yet but it looked as expected in the preview window and the Gerber Viewer.

@UserSupport, 3 years on and this problem is still not fixed. From @cjohnson's reply in this topic: [https://easyeda.com/forum/topic/Bottom-layer-is-without-solder-mask-24e9387b2fe5448eb93a1fd75e071872](https://easyeda.com/forum/topic/Bottom-layer-is-without-solder-mask-24e9387b2fe5448eb93a1fd75e071872)<br> <br> "When EasyEDA generates the files, it sees that there are no "exposures" on the bottom layer, so it just doesn't generate a file correctly that shows "no exposure." I have experimented with placing a multilayer pad with a negative soldermask expansion (to ensure that the pad is completely covered with soldermask) and can confirm that the statement above is correct. What I have found is that if the negative soldermask is large enough to cover the whole of the pad area but is less that the radius of the pad (so that the hypothetical soldermask covering the hole through the pad itself has a small area where the soldermask is not removed) then if that pad is used in place of a via then the missing soldermask is correctly created. The problem then is that, because the pad is not actually a via, if spokes are enabled in the copper area then this pad will generate spokes whereas a true via does not. You can try this using the footprint: MULTILAYER\_PAD\_AS\_VIA  **Please fix this bug.** Thanks.

Here's a workaround. As @cjohnson has described in his bug report - placing an aperture in the soldermask layer that is not being properly created seems to force it to be generated correctly. Assuming that the PCB has at least one hole in it, whether it is for a via, pad, an unplated hole for something like a screw, connector or pot, then if a soldermask aperture with a diameter of less than the diameter of any one of the existing holes is placed in the centre of the selected hole: the missing soldermask layer appears to be correctly generated. This allows the problem to be worked around without the additional aperture in the soldermask layer exposing the copper or substrate material.